Pre-synthesis resource generation and estimation for transport-triggered architecture (TTA)-like architecture

Abstract

Electronic system level (ESL) design is widely adopted in today’s embedded systems development projects to cope with increasing system complexity and shrinking time-to-market. Even though functional verification can be performed at the system level and early design stage efficiently, it is still difficult to perform accurate hardware resource estimation. In this paper, we consider the problem of mapping an input high-level algorithm in C into hardware implementation based on the transport-triggered architecture (TTA)-like architecture, and present effective techniques for predicting architectural-level parameters and gate-level resource consumption without going through the lengthy hardware synthesis process in order to facilitate rapid design space exploration. We use some common DSP algorithms and a complete industry GPS application to show that our resource estimation results match the actual results from hardware synthesis very well, and they can be used in a feedback loop to optimize the input algorithm specification in C, e.g., the total gate count of the GPS application is reduced by 25% compared to the original input algorithm specification. In addition, the simulation results of the generated hardware descriptions in Verilog also show good agreement with the execution results of the original GPS program in C.