An approach for reusing test source of an IP to reduce verification effort

Abstract

Over the past few years, the Integrated circuits design and verification has become increasingly complex. Industry, to overcome this problem has shifted to Electronic System Level (ESL) design flow. The ESL design at higher level of abstraction is called Virtual System Prototype (VSP). Each Intellectual Property (IP) in VSP should be verified Block level (Standalone verification) and in system level. This paper deals with reusability of the test cases for an IP in module level verification and system level verification. The aim is to reduce the test effort for same test in different verification environment. A common test source is developed for ADC IP and the functionality is verified in the standalone and system level verification environments by reusing the test cases.