A scalable and configurable Multiprocessor System-on-Chip (MPSoC) virtual platform for hardware and software co-design and co-verification

Abstract

This paper defines a scalable and configurable Multiprocessor System-on-Chip virtual platform for hardware and software co-design and co-verification in Electronic System Level (ESL) design. It includes the integration of an Instruction Set Simulator (ISS) to the virtual platform, Transaction Level Modeling (TLM), IP (Intellectual Property) block design in high level of abstraction, and hardware and software partitioning. The virtual platform has been tested to develop and successfully tested to develop and run an AES-128 encryption software. The architecture of the virtual platform consist of multiple ARM Cortex-M0 processor, bus-based and Mesh NoC (Network-on-Chip) architecture, and IP (peripherals) to support the system. Lotus-G displays its capability to fill the gap between hardware and software team in ESL design and verification flow. It provides the software team with a platform which enables them to start software development and testing early before the RTL platform is ready. The virtual platform also gives the hardware team a golden reference model that acts as the functional specification reference during hardware design and verification.