Design Of Electronic Packages Research Articles

Data-driven electronic packaging structure inverse design with an adaptive surrogate model

PurposeThe conventional design method relies on a priori knowledge, which limits the rapid and efficient development of electronic packaging structures. The purpose of this study is to propose a hybrid method of data-driven inverse design, which couples adaptive surrogate model technology with optimization algorithm to to enable an efficient and accurate inverse design of electronic packaging structures.Design/methodology/approachThe multisurrogate accumulative local error-based ensemble forward prediction model is proposed to predict the performance properties of the packaging structure. As the forward prediction model is adaptive, it can identify respond to sensitive regions of design space and sample more design points in those regions, getting the trade-off between accuracy and computation resources. In addition, the forward prediction model uses the average ensemble method to mitigate the accuracy degradation caused by poor individual surrogate performance. The Particle Swarm Optimization algorithm is then coupled with the forward prediction model for the inverse design of the electronic packaging structure.FindingsBenchmark testing demonstrated the superior approximate performance of the proposed ensemble model. Two engineering cases have shown that using the proposed method for inverse design has significant computational savings while ensuring design accuracy. In addition, the proposed method is capable of outputting multiple structure parameters according to the expected performance and can design the packaging structure based on its extreme performance.Originality/valueBecause of its data-driven nature, the inverse design method proposed also has potential applications in other scientific fields related to optimization and inverse design.

CFD Modeling of the Effect of the Air- Cooling on Electronic Heat Sources

ABSTRACT The target of this research is to study the performance of air cooling of an electronic cabinet including a heat sources (electronic circuit boards) by using axial fan. The cabinet is cooled from the top by one port while the lower and side walls temperature is kept constant. The effect of inlet and outlet air ports positions in the cabinet is considered. In this work, Icepak4.2.8 package is used in the numerical study. The steady of the 3D incompressible viscous flow problem is solved by using the Icepak package. Various air cooling geometries are applied. Specific conditions for each case are defined, and the computational fluid dynamics is provided for three different groups containing six cases of local inlet and outlet ports. The results are performed for cooling effect factor (CEF). KEYWORDS: Air cooling, Electronic circuit, CFD, Icepak. INTRODUCTION he design of cooling systems for electronic equipment is getting very involved and challenging due to an increase in demand for faster and more reliable electronic systems. Therefore, robust and more efficient design and optimization methodologies are required. Natural convection heat transfer is an important phenomenon in engineering systems due to its wide application in electronics cooling, heat exchangers, and double pane windows. Enhancement of heat transfer in these systems is essential from the industrial and energy saving perspectives. The low thermal conductivity of conventional heat transfer fluids, such as water puts a primary limitation on the performance and the compactness of thermal systems. As a result, different cooling technologies have been developed to efficiently remove the heat from these components. The use of a liquid coolant has become attractive due to the higher heat transfer coefficient achieved as compared to air-cooling. Coolants are used in both single phase and two-phase applications. A single phase cooling loop consists of a pump, a heat exchanger (cold plate/mini- or microchannels), and a heat sink (radiator with a fan or a liquid-to-liquid heat exchanger with chilled water cooling). The heat source in the electronics system is attached to the heat exchanger. Liquid coolants are also used in two-phase systems, such as heat pipes, thermo-siphons, sub-cooled boiling, spray cooling, and direct immersion systems for cooling of electronics [1]. The rapid development in the design of electronic packages for modern high-speed computers has led to the demand for new and reliable methods of chip cooling. As stated by Mahalingam and Berg [2], the averaged dissipating heat flux can be up to 25 W/cm² for high-speed electronic components. However, the conventional natural or forced convection cooling methods are only capable of removing small heat fluxes per unit temperature difference, about 0.001 W/cm².

AV1 Arithmetic Encoder Design on Open-Source EDA

With the increasing demand for video transmission through the Internet, video coding has become a key technology to allow this market's growth at a reduced cost. Moreover, with the inception of higher video resolutions (e.g., 4K, 8K) and their impact on video size, new video coding standards must tackle this issue to reduce video traffic demand on the global internet infrastructure. The AV1, a recently released royalties-free video coding format created by the Alliance for Open Media (AOMedia), reaches great compression rates but cannot accomplish real-time execution on software-only implementations due to its high complexity. This paper presents and analyzes AE-AV1, a high-performance 4-stage pipelined architecture to accelerate the AV1 arithmetic encoding process (part of the entropy encoder block) and make it capable of real-time execution. For the analysis, this work aims to rely on fully open-source Electronic Design Automation (EDA) tools and Package Design Kits (PDKs).

Shock and impact reliability of electronic assemblies with perimeter vs full array layouts: A numerical comparative study

Abstract This study aims to assess the effect of the solder joint array layouts, including full and peripheral designs, on the mechanical response and reliability of electronic packages subjected to shock and impact loadings. Linear and nonlinear finite element simulations using the global-local modeling technique are employed to perform the analysis. Several peripheral array configurations are considered and compared to the full array systems. The results showed that, for optimum electronic package designs in terms of reliability and cost, it is highly recommended to use peripheral packages having three or four rows of solder interconnects in electronic systems under shock and impact loadings.

Simulation of a point-to-point wireless communication with XBEE technology for monitoring environmental variables

This article describes the simulation of a unidirectional point-to-point radio frequency (RF) Wireless communication between two electronic circuits with XBEE technology, using the electronic design software PROTEUS V8.8. In the same worksheet in the ISIS graphical interface, the two electronic circuits were implemented, one was called the transmitter circuit and the other the receiver circuit. A Microchip® PIC16F877A microcontroller and an XBEE module are the main devices of each of the electronic circuits, to establish wireless communication by RF. The PIC microcontroller of the transmitter circuit was used as a DAQ data acquisition device, to measure the temperature of two analog sensors, the LM35 and the TMP36, and three digital sensors DS1621. The temperature data was sent from the transmitter circuit to the receiver circuit in character strings, using asynchronous serial communication. A programming algorithm was implemented for the PIC microcontroller of the receiver circuit, to receive and identify the temperature data. The development of this simulation is the basis to implement a wireless sensor network (WSN) with XBEE technology in the future.

Application of EDA Technology in Electronic Engineering Design

The rapid development of EDA technology makes it more and more widely used in modern electronic system design, 
 including IC design, circuit board wiring, function verification and simulation, and testing.Electronic engineering design is the core 
 course of cultivating electrical information majors, which helps cultivate students’ engineering ability, practical ability, innovative 
 consciousness, systematic thinking, etc. Through the application of EDA Technology in all links of course implementation, 
 including design scheme selection, unit circuit design and system debugging, the correctness and reliability of circuit design are 
 greatly improved, and the application ability of students’ electronic design software is greatly exercised.

Additively Manufactured Extreme Temperature Electronics Packaging

Abstract There is growing interest in extreme temperature electronics to support the mission needs to sense, actuate, and communicate at temperatures beyond the normal range of operations in commercial and military applications. Reliable packaging in the temperature range of more than 300°C has been demonstrated using ceramic multi-chip modules using conventional hybrid circuit technology. This approach typically requires high NRE costs and lead time. Additive manufacturing processes of metals, ceramics, conductors, and dielectrics provides a digital transformation of hybrid circuit manufacturing technology that reduces time and cost for packaging with the added benefits of novel 3D structures and embedded features. This report presents the results of testing to characterize important electrical and mechanical properties of additively manufactured packaging materials (substrates, conductor, dielectrics) and die interconnect methods needed for 300 to 750 °C electronic packaging designs.

Influence of Reflow Profile on Thermal Fatigue Behaviors of Solder Ball Joints

In electronic package design, solder joints are critical in providing electrical connections and mechanical support. The mechanical reliability of interconnection is dependent on the microstructure evolution that occurs within the solder due to the temperature changes primarily from transportation, storage, and device usage. In this study, two solder alloys, eutectic 63Sn37Pb and lead-free 95.5Sn4.0Ag0.5Cu, were tested for their thermal fatigue reliability and were observed for changes in microstructure. The different microstructures of each sample were created by controlling the cooling rate, fast or slow, during reflow. To characterize reliability, the samples endured thermal cycling − 40-125 °C until electrical failure. Finite element analysis was used to predict the primary deformation mechanism. The microstructure was inspected by cross-sectioning the solder samples using scanning electron microscopy with energy-dispersive x-ray spectroscopy. It was found that by controlling the microstructure development through the reflow rate, the solder joint’s thermal fatigue life can be extended, and concurrently, the reliability of the electronic package can be enhanced.

EPEPS 2020 - The Design and Analysis Frontier of Electronic Packaging

EPEPS 2020 - The Design and Analysis Frontier of Electronic Packaging

Experimental and Modeling Study on Delamination Risks for Refinished Electronic Packages Under Hot Solder Dip Loads

For electronic packaging engineers in the high-reliability sectors, such as aerospace, defense, oil & gas, etc., the use of commercial off-the-shelf components offers significant advantages due to their high availability, fast delivery time, and low cost. However, these components pose significant reliability challenges due to the risks associated with tin whisker formation and uncertainty on the long-term reliability of lead-free solders. For addressing these risks, the hot solder dip process is used to refinish the package by replacing lead-free solder finishes with lead-based finishes to meet the stringent packaging and assembly requirements for these sectors, which are exempt from restriction of hazardous substances (RoHS) legislation. But the hot solder dip process is an extra process that exposes the package to an additional thermal load, which will result in thermomechanical stresses that need to be properly understood and controlled. For addressing this challenge, a multidisciplinary methodology combining thermomechanical models with “dip-to-destroy” experiments and scanning acoustic microscopy has been developed to identify the risk of package material delamination for a number of package designs. Results show that the developed models can predict delamination risks for a range of imposed thermal gradients. Electronic package designs with a direct heat path from dipped terminations to the internals of the package show a higher risk of overstress-induced delamination, and this failure is generally driven by the high-temperature excursion above the glass transition point of the molding compound. The novelty and significance of these findings is that the derived methodology can be used by electronic packaging designers to optimize the thermal parameters of the hot-solder-dip process so that subsequent refinished packages can meet the stringent high-reliability requirements for these sectors.

Thermal spreading resistance of heat sources on rectangular flux channel under non-uniform convective cooling

A general solution, based on the method of separation of variables, for the temperature distribution of an orthotropic rectangular substrate heated by heat sources on one side and cooled with a non-uniform heat transfer coefficient on the opposite side is presented. A system of infinitely many algebraic equations obtained by taking advantage of the orthogonality property is encountered and must be solved for the solution coefficients. An iteration method is proposed to overcome this difficulty. Such an analytical solution provides an easy and efficient way to explore the influence of relevant parameters. A fitting curve to the analytical predictions against interested parameters can be next obtained, if desired, to replace the troublesome infinite-series solution and employed in the resistor-capacitor thermal models for predicting the heat dissipation power of electronic packaging designs.

Accelerated Thermal Depolymerization of Cyclic Polyphthalaldehyde with a Polymeric Thermoacid Generator.

Thermally triggerable polymer films that degrade at modest temperatures (≈85 °C) are created from a blend of cyclic polyphthalaldehyde (cPPA) and a polymeric thermoacid generator, poly(vinyl tert-butyl carbonate sulfone) (PVtBCS). PVtBCS depolymerizes when heated, generating acid which initiates the depolymerization of cPPA into volatile byproducts. The mass loss onset for 2 wt% PVtBCS/cPPA is 22 °C lower than the onset for neat cPPA alone in dynamic thermogravimetric analysis experiments. Increased concentrations of PVtBCS increase the rate of depolymerization of cPPA. Raman spectroscopy reveals that the monomer, o-phthalaldehyde, is the main depolymerization product of the acid-catalyzed depolymerization of cPPA. The PVtBCS/cPPA blend is a promising material for the design and manufacture of transient electronic packaging and polymers.

Material Selection for Interfacial Bond Layer in Electronic Packaging

In electronic packaging, typically two or more thin dissimilar plates or layers are bonded together by an extremely thin adhesive bond layer. Electronic assemblies are usually operated under high power conditions which predictably produces a high temperature environment in the electronic devices. Therefore, thermal mismatch shear and peeling stress inevitably arise at the interfaces of the bonded dissimilar materials due to differences in Coefficient of Thermal Expansion (CTE) typically during the high temperature change in the bond process. As a result, delamination failure may occur during manufacturing, machining, and field use. As such, these thermo-mechanical stresses play a very significant role in the design and reliability of the electronic packaging assembly. Consequently, critical investigations of interfacial stresses under variable load conditions in composite structure can result in a better design of electronic packaging with higher reliability and minimize or eliminate the risk of functional failure. In order to formulize bond material selection, analytical studies are carried out in order to study the influence of bond layer parameters on interfacial thermal stresses of a given package. These parameters include Coefficient of thermal expansion (CTE), poison’s ratio, temperature, thickness, and stiffness (compliant and stiff) of the bond layer. From the study, stiffness and bond layer thickness are identified as the key parameters influencing interfacial shearing and peeling stresses. The other parameters namely CTE, poisons ratio has shown insignificant influence on interfacial stresses due to the very thin section of bond layer compared to the top and bottom layers. The results also show that the interfacial stresses increases proportionally with the increase of temperature in the layers. Therefore, it is very important that the temperature is maintained as low as possible during the chip manufacturing and operating stages. Since only two parameters namely stiffness and bond layer thickness are identified as the key parameters, the interface thermal mismatch stresses can be reduced or eliminated by controlling these two parameters only. Therefore the identification of suitable bond layer parameters selection with reasonable accuracy is possible even without performing optimization process. Finally, this paper proposes a Metal Matrix Composite (MMC) bond material selection approach using rule of mixture material design. The outcome of this research can be seen in the forms of practical and beneficial tools for interfacial stress evaluation and physical design and fabrication of layered assemblies. The Engineers can utilize this research outcome in conjunction with guidelines for electronic packaging under variable thermal properties of layered composites.

Thermal Analysis of Solder Joint Based on Eddy Current Pulsed Thermography

Solder joint provides electronic and mechanical connections between components and substrate. Overheating and excessive temperature gradient can cause solder joint failures and then make the whole system break down. Thus, thermal analysis has been the hotspot in reliability evaluation of electronic packaging. This paper proposes eddy current pulsed thermography (ECPT) to investigate thermal transfer through solder joint in a surface mounted device (SMD). A 3-D electromagnetic-thermal model was built, and the ECPT system was established to analyze transient temperature distribution on the pin surface. This model introduced pseudo soldering and evaluated its impacts on thermal conduction. Thermal resistance of solder joint was calculated to characterize different pseudo soldering defects. With pseudo soldering acreage increased, thermal resistance had an approximate quadratic rise. Both simulation and experimental results indicate that the surface temperature gradually decreases with the increase of pseudo soldering acreage. This ECPT method could be applied to the thermal analysis of solder joint in SMD, and it also could provide guidance for thermal design or reliability evaluation of electronic packages.

H $${^{+}}$$ + -ion-sensitive FET macromodel in LTSPICE IV

pH measurements are widely used in biomedical engineering, agriculture, environmental studies, the food industry, etc. In biomedical and healthcare research, it is said that all aqueous samples have their pH tested at some point in their lifecycle for evaluation of wound healing or susceptibility, diagnosis of diseases, cellular internalization, etc. The ion-sensitive field-effect transistor (ISFET) in blank form is capable of pH measurements. When its gate comes into contact with an electrolyte, the activity of ions dissolved in the electrolyte is converted to an electrical potential while releasing free electrons. Such use of the ISFET has become popular, as it allows sensing, preprocessing, and computational circuitry to be encapsulated on a single chip, enabling miniaturization and portability. LTSPICE IV is a computational electronic design software package that facilitates design and simulation of circuits before their costly fabrication. Despite its popularity, the ISFET is still not available in the component library of LTSPICE IV. Hence, we propose herein an ISFET macromodel to contribute as a new subcircuit block for the LTSPICE IV component library, to enable design of ISFET-based sensors or microsystems. A mathematical model for the ISFET is first derived and programmed into netlists, from which a macromodel is constructed. This ISFET macromodel is tested by using it to generate characteristic graphs relating important ISFET parameterization variables. Simulation results show that, at low pH, when the H$${^{+}}$$+ ion concentration in the electrolyte is high, higher drain current is generated, similar to the results of the mathematical model. As a consequence, from the simulation of the drain current with respect to a reference voltage, at higher pH values the first-order response is found to be more sluggish with slow turn-on of the drain current. Moreover, the drain voltage is found to suppress the sensitivity (reference threshold voltage/pH) of the ISFET. According to the simulations of the drain current and pH, reference voltages of 1.0 and 1.5 V result in high linearity and sensitivity. According to the simulations of the drain current and drain voltage, a reference voltage of 1.5 V is found to be good in terms of operational linearity and sensitivity.

An Evaluation Method for Tensile Characteristics of Cu/Sn IMCs Using Miniature Composite Solder Specimen

In design of electronic packages, finite-element method (FEM) analysis for evaluating the strength and reliability of solder joints should be conducted with consideration of the presence of Cu/Sn intermetallic compounds (IMCs) generated at the interface between solder and copper wiring. To conduct such analysis accurately, the deformation characteristics of Cu/Sn IMCs must be clarified by conducting tensile tests. This paper describes a method to evaluate tensile characteristics of Cu/Sn IMCs. The method employs a composite specimen with first outer layer of Cu, second layer of Cu/Sn IMCs, and core of Sn-3.0Ag-0.5Cu lead-free solder. The specimen is made by a method in which a copper-plated solder specimen is heat treated at 453 K to generate Cu/Sn IMCs between the solder and copper. Tensile tests were conducted using the composite specimen. After the tests, the fracture appearance and characteristics of the stress–strain relations of the specimens were investigated. Based on the results, a numerical method based on the rule of mixtures (ROM) is proposed to estimate the stress–strain relation of Cu/Sn IMCs under tensile loading.

Prediction of interfacial reaction products between metals with same lattice structure through thermodynamic modeling

Interfacial reactions exert crucial effect on the performance of soldering joints. Prediction of the first phase formed at the interface between metals benefit the design of electronic packaging. Based on our previous work, a new scheme is developed in this paper, which aims at predicting phase formation of the interface reaction between metals with the same lattice structure. In the new scheme, the conventional principle considering both the thermodynamic and kinetic factors is employed. A criterion is introduced for the case where a spinodal decomposition exists in the starting solution when the local equilibrium assumption is still valid. Another new criterion involving only nucleation driving force and entropy change is proposed for the case where no spinodal decomposition occurs and the assumption of local equilibrium is no longer valid. The validity of these criteria has been confirmed when applied to predict the intermetallic compound (IMC) formed in the binary diffusion couples such as Al/Cu, Al/Pt, Al/Au, and Co/Zn.

Response Spectrum Analysis of Printed Circuit Boards Subjected to Shock Loads

A spacecraft consists of a number of electronic packages to meet the functional requirements. An electronic package is generally an assembly of printed circuit boards placed in a mechanical housing. A number of electronic components are mounted on the printed circuit board (PCB). A spacecraft experiences various types of loads during its launch such as vibration, acoustic and shock loads. Prediction of response for printed circuit boards due to shock loads is important for mechanical design and reliability of electronic packages. The modeling and analysis of printed circuit boards is required for accurate prediction of response due to shock loads. The validated finite element model of the PCB can be adopted to perform response spectrum analysis. Shock response spectrum analysis of printed circuit boards subjected to a half-sine pulse excitation is carried out using finite element method. The objective of this paper is to predict the shock response spectrum of a printed circuit board due to launch environment. The analysis results are validated by conducting experimental tests of PCB.

Vibration Response Prediction of the Printed Circuit Boards Using Experimentally Validated Finite Element Model

A spacecraft consists of a number of mechanical and electronic sub-assemblies. An electronic package is consists of printed circuit boards placed in mechanical housings which are stacked together. Electronic components are mounted on the printed circuit board (PCB). A spacecraft experiences various types of mechanical loads during its launch such as vibration, acoustic and shock loads. The understanding of dynamic behaviour provides valuable insight to a design engineer, to improve the mechanical design and product reliability when used in harsh vibration condition. Generally electronic package design for vibration loads is verified by conducting tests on actual hardware.This paper addresses on using basic FEA tool to accurately investigate the dynamic characteristics of the PCB and avoid costly testing methods which require hardware. Here the normal modes & frequency response functions (FRF) of PCB are determined and validated using vibration test on PCB. The validated model is used to predict vibration response for random vibration input. It is shown here how the responses are accurately predicted for random vibration input for a design parameter variation of PCB. The results are also validated using vibration test on PCB.

A Spatial-Random-Process Based Multidisciplinary System Uncertainty Propagation Approach With Model Uncertainty

The performance of a multidisciplinary system is inevitably affected by various sources of uncertainties, usually categorized as aleatory (e.g., input variability) or epistemic (e.g., model uncertainty) uncertainty. In the framework of design under uncertainty, all sources of uncertainties should be aggregated to assess the uncertainty of system quantities of interest (QOIs). In a multidisciplinary design system, uncertainty propagation (UP) refers to the analysis that quantifies the overall uncertainty of system QOIs resulting from all sources of aleatory and epistemic uncertainty originating in the individual disciplines. However, due to the complexity of multidisciplinary simulation, especially the coupling relationships between individual disciplines, many UP approaches in the existing literature only consider aleatory uncertainty and ignore the impact of epistemic uncertainty. In this paper, we address the issue of efficient uncertainty quantification of system QOIs considering both aleatory and epistemic uncertainties. We propose a spatial-random-process (SRP) based multidisciplinary uncertainty analysis (MUA) method that, subsequent to SRP-based disciplinary model uncertainty quantification, fully utilizes the structure of SRP emulators and leads to compact analytical formulas for assessing statistical moments of uncertain QOIs. The proposed method is applied to a benchmark electronic packaging design problem. The estimated low-order statistical moments of the QOIs are compared to the results from Monte Carlo simulations (MCSs) to demonstrate the effectiveness of the method. The UP result is then used to facilitate the robust design optimization of the electronic packaging system.