Electromigration Performance Research Articles

Electromigration of Flat and Bent Copper Lines Patterned with a Plasma-Based Etch Process

The electromigration performance of the copper line, which was patterned by a unique plasma-based etch process, was investigated with the accelerated isothermal lifetime method. The failure analysis result showed that voids originated along the copper–dielectric interface as well as at copper grain-boundary junction points. During the electromigration test, a large stress existed between the copper layer and the silicon nitride cap layer, which caused the cap layer cracking and copper extrusion. When the copper line was mechanically bent, the activation energy was lowered and the void distribution pattern was drastically changed. The lifetime of the copper line was shortened with the applied bending stress. Therefore, for large-area flexible electronics applications, the reliability of the copper interconnect line is an important factor that needs to be addressed.

Solder Bump Electromigration and CPI Challenges in Low-k Devices

Understanding and managing both chip-to-package interaction (CPI) and solder bump electromigration (EM) in new designs is becoming an increasing challenge for flip chip plastic ball grid array (FCPBGA) packaging. Requirements for state-of-the-art device technologies drive smaller features, higher power and RoHS compliance (Pb-free product). It will be shown that the optimal attributes for Pb-free solder bump EM performance often are diametrically opposed to the design parameters that improve CPI robustness in structures comprised of low-k dielectric materials.

Electromigration Improvement for Advanced Technology Nodes

Electromigration (EM) reliability has become a growing concern for Cu interconnects in advanced technology nodes. The interface between the dielectric diffusion barrier (SiCN) and copper, metal barrier quality and metallization homogeneity are all critical to EM performance. Our EM enhancement investigation has focused on improving the SiCN/Cu interface, metal barrier quality and metallization homogeneity while mitigating the process integration risk and cost. Multiple processes developed at Novellus have demonstrated significant EM improvement without compromising stress migration or dielectric reliability. The results of these process developments and the mechanisms of EM improvement will be discussed in this paper.

A copper-dielectric cap interface with high resistance to electromigration for high performance semiconductor devices

In highly integrated semiconductor devices the time to failure of copper interconnects strongly depends on the properties of the copper-dielectric cap interface. In this work a production capable preparation of copper-dielectric cap interfaces with a high resistance to electromigration (EM) has been developed for 90 and 65 nm dual damascene technologies. With a new soft silicidation pretreatment of the copper metallization followed by a deposition of a SiCN or SiN cap the EM lifetime could be improved 3.5× referring to a standard SiCN capping process. The new pretreatment enables the formation of an epitaxial copper silicide layer on top of the copper metal lines which is seen as the key factor of the lifetime improvement. The new kind of cap layer process enables the lifetime improvement with only negligible increase of metal sheet resistance. The surface damage of copper and the low k inter-level dielectric which is typically caused during the copper precleaning could be minimized significantly. It is shown that there is no linear correlation between adhesion to copper and electromigration performance.

Effect of Sn grain orientation on electromigration degradation mechanism in high Sn-based Pb-free solders

Electromigration induced damage strongly depends on Sn-grain orientation in Pb-free solders. Rapid depletion of intermetallic compounds and under bump metallurgy led to significant damages caused by the fast diffusion of Cu and Ni along the c axis of Sn crystals. When the c axis of Sn grain is not aligned with the current direction, electromigration (EM) damage is dominated by Sn self-diffusion, which takes longer to occur. This is a direct proof of the highly anisotropic diffusion behavior in Sn. Due to the presence of twin structures and stable Ag3Sn network, SnAg(Cu) solders are less susceptible to grain orientation effects and showed better EM performance than SnCu solders.

Effect of Interfacial Condition on Electromigration for Narrow and Wide Copper Interconnects

The sub-micron damascene interconnects, electromigration is mainly due to the diffusion at the interfaces of Cu with liner or dielectric capping layer. Many reports have shown that Cu/capping dielectric is the dominant interface. Experiments were performed to study the effect of the interfacial conditions of Cu/capping dielectric material on electromigration for narrow and wide Cu lines. The results revealed significant differences in electromigration behavior of via-fed upper and lower layer damascene test structures. For upper layer test structure, the capping layer and plasma surface treatment significantly dominated EM performance for different line width structures. In the case of lower layer test structure, the electromigration time to failure was found to be influenced by the capping layer and via process, and it remained unaffected by the plasma surface treatment for the narrow Cu line. For the wide line width (3X), electromigration performance was influenced by the current crowding on via-bottom.

Using a Barrier Layer to Inhibit Ti/Oxide Reaction to Reduce RC Delay and Improve Electromigration in Al-Cu/Ti/W Interconnect for High Power Analog and Mixed Signal Applications

ABSTRACTIn this paper, we report a novel method to improve aluminum interconnect electromigration performance, reduce metal line sheet resistance (Rs) and reduce via contact resistance (Rc) in a minimum pitch design. We report the effects of bottom redundancy layers on electrical line and via resistance and upstream electromigration performance. We studied 4 metallization stacks: (I) Ti/TiN/AlCu/Ti/TiN, (II) Ti/TiN/Ti/AlCu/Ti/TiN (annealed at 400°C for 20 minutes), (III) a flash process/stack I, (IV) stack III with aluminum deposition temperature of 250°C. Aluminum deposition temperature in stacks I, II, and III are 200°C. Bottom Ti/TiN, AlCu, and Top Ti/TiN layers have the same thickness for all these stacks. Metal line Rs and via contact resistances (Rc) of stack IV are 5% and 10% lower, respectively, than stack I. Stack II metal line sheet resistance is 15% higher than stack I, which is attributed to Al consumption in the TiAl3 formation during 400°C/20minutes annealing. Electromigration performance is best with stack IV followed by III, II, then I.

Electromigration of Cu Interconnect Lines Prepared by a Plasma-based Etch Process

ABSTRACTThe electromigration performance of Cu lines patterned by a Cl2 plasma-based etch process has been studied with the accelerated isothermal lifetime test. An electromigration activation energy of 0.6 eV and a current density acceleration exponent of 2.7 were obtained. Both the copper-silicon nitride cap layer interface and the copper grain boundary were active diffusion paths. The applied mechanical bending stress changed the electromigration void distribution in the film, which leaded to the shorter lifetime and lower activation energy.

A method for AlCu interconnect electromigration performance predicting and monitoring

The physical properties of (bottom)Si/SiO2/Ti(top) and (bottom)Si/SiO2/Ti/TiN/Al(0.5wt.% Cu)(top) structures by different processes were compared and studied. The resistivities of thin Ti films and the reflectivities of thin Al alloy films were found to correlate to their microstructure as well as the mean time to fail (MTTF) in electromigration (EM) testing. A method to predict and monitor the EM performance of the AlCu interconnects was proposed.

Reservoir effect in SiCN capped copper/SiO 2 interconnects

By analyzing electromigration in large lines, the reservoir effect due to via connecting matrices has been studied evidencing the key role of the (via + via inter-space) area parameter to gain lifetime. This extra-lifetime can be converted into effective current density increase, useful for circuits very demanding in current, depending on metal level. The understanding of the reservoir effect finally allowed the comparison of electromigration performance of lines of different width. It pointed out that the lifetime decreases with increasing line width, which evidences the copper diffusion at grain boundaries as mechanism.

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.

Evaluation of a PECVD advanced barrier ( k = 3.7) for 32 nm CMOS technology and below

An advanced dielectric barrier proposed for sub-45 nm CMOS technology nodes is firstly characterized on 300 mm full sheet wafers. The barrier is a bi-layer deposited by PECVD. The copper diffusion barrier property is ensured by a depositing dense initiation layer with the efficiency of a standard SiCN barrier ( k = 5.0). The top layer, thicker, with lower density, enables the decrease of the barrier k-value to 3.66 and plays the role of etch stop layer. Combined with a PECVD porous a-SiOC:H dielectric ( k-value = 2.5), the advanced dielectric barrier is successfully integrated in a C65 dual damascene architecture reaching a 3% gain in RC. A high via chain resistance yield is evidence of good via opening. Finally, the advanced barrier shows the same electromigration performance than the standard SiCN barrier.

Current Challenges with Copper Interconnects

In the integrated circuit industry, aluminum-based interconnects and oxide interlayer dielectrics have been replaced with copper interconnects in a dual inlaid architecture and with low-K dielectrics. Inlaid Cu lines offer higher conductivity, improved electromigration performance and a reduced cost of manufacturing. In this manuscript, the current challenges with integrating Cu in high-performance integrated circuits are detailed. As technologies scale, the many steps in the integrated process flow cannot be viewed as independent. The interactions between process steps (module interactions) that must be considered will be discussed. The development of a reliable and manufacturable technology requires a fundamental understanding of these interactions. A process-oriented finite element model (FEM) will be presented to capture the effect of individual process steps on the stress evolution during processing. Finally, the future trends for Cu interconnect will be suggested.

Effects of Al doping on the electromigration performance of damascene Cu interconnects

We report the effects of Al doping on electromigration in damascene Cu interconnects. Al doping was performed by thermal diffusion from a CuAl seed layer positioned underneath the Cu interconnects. To investigate the dependencies of the Al concentration, the seed CuAl layer thickness was increased from 40to90nm on a planar surface. The effects of Al doping on the incubation time, drift velocity, and critical product of electromigration were investigated. The drift velocity of Cu mass transport in CuAl alloys decreases with an increase in the concentration of Al atoms. The observed critical product of electromigration is 1500A∕cm, and it is independent of the Al concentration. The measured activation energies of the normalized drift velocities for CuAl seed layer thicknesses of 40, 60, and 90nm are 1.2, 1.4, and 1.5eV, respectively. The Al concentrations at Cu∕SiCN interface, grain boundary, Ta∕Cu interface, and bulk were investigated along the length of a line by the electron microprobe technique. The time dependent Al concentration at the Cu∕SiCN interface near the cathode end of the line is observed. These characteristics indicate that the doped Al affects the electromigration-induced Cu diffusion and does not affect the driving force.

Probing into the asymmetric nature of electromigration performance of submicron interconnect via structure

The void locations of via electromigration failures for multi-level dual damascene copper interconnect structure are highly asymmetric with respect to the current flow direction. In this work, finite element analysis is performed to investigate the nature of the asymmetries, and to identify the likely failure locations in the via structures at different test conditions. By coupling the current density, temperature and the stress fields in the analysis, and using the site with maximum atomic flux divergence as the void location site, a good correlation between the model predictions and experimental observations is obtained.

Improved electromigration failure in Al based interconnects

AbstractElectromigration (EM) failure in Al interconnects is significantly improved by inserting a WN film between Al and the interlayer dielectric: over 90% of test samples failed with the Al/TiN/Ti interconnects, whereas the failure rate of the Al film on WN is reduced to less than 13% under the stress con‐ ditions of 9 MA/cm2 and 225 °C, and the EM lifetime is also much extended at the same conditions. Experimental results suggest that higher activation energy, no hillocks and compressive stress are responsible for the improved electromigration performance in the Al/WN interconnect. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Correlation between electromigration and Cu-contact angle after de-wetting

An alternative, and quicker way of assessing the electromigration (EM) reliability of Cu interconnects is investigated. It is based on observations of de-wetting and contact angle measurement of Cu thin films. Contact angle results are compared to EM tests, and the correlation between Cu de-wetting and electromigration performance is demonstrated. PVD TaN x /Ta or ALD TaN barrier layers are tested, while the seed layer is either pure copper or a CuAl 1 at%. In addition, three types of barrier treatments are investigated: different exposure times to plasma of ALD TaN; tantalum flash between ALD TaN and pure copper seed deposition; ALD TaN exposure to atmospheric oxygen.

Improved electrical and reliability performance of 65 nm interconnects with new barrier integration schemes

Ta (N)/Ta bi-layer is a commonly used barrier in damascene copper interconnects for 90 nm and 65 nm technology nodes. A new barrier integration scheme so-called punch-through is currently used for 65 nm node. The main feature of the new deposition scheme is to introduce an etch-back step between the Ta (N) layer deposition and the Ta layer deposition. This intermediate etch step cleans up the bottom of via and also partially etch the underlying copper line with a depth of few nanometers. This step changes dramatically the bottom of via shape leading to via anchoring into the underlying copper line. In this paper we compare punch-through versus no punch-through approach. We show that the punch-through leads to a lower via resistance and to a tighter via resistance distribution, while keeping line resistance similar. We show that via anchoring into the underlying copper line coupled with a better tantalum step coverage dramatically reduces stress migration effect and also improves electro-migration performances at 65 nm technology node.

Issues related to the implementation of Pb-free electronic solders in consumer electronics

Consumer electronic applications are the primary target of the Pb-free initiative and package assembly and performance is affected by the move from eutectic Sn-Pb to Pb-free solder alloys. This paper outlines the key issues and mitigation possibilities for package assembly using Pb-free solders: High temperature reflow, Interfacial reactions, and Reliability. At the high temperatures required to reflow Pb-free alloys, moisture absorbed into the package can result in delamination and failure. The reaction of the Pb-free solder with Ni and Cu metallizations results in interfacial intermetallics that are not significantly thicker than with Sn-Pb but provide a path for fracture under mechanical loading due to the increased strength of the Pb-free alloys. The reliability issues discussed include thermomechanical fatigue, mechanical shock, electromigration and whiskering. The Pb-free alloys tend to improve thermomechanical fatigue and electromigration performance but are detrimental to mechanical shock and whiskering. Design trade-offs must be made to successfully implement Pb-free alloys into consumer applications.

Experimental investigation on the impact of stress free temperature on the electromigration performance of copper dual damascene submicron interconnect

Electromigration experiments are conducted for submicron dual damascene copper lower level interconnect samples of different stress free temperatures. The electromigration life-time is found to be strongly depend on the stress state of the metallization and the stress gradient that exist due to thermal mismatch of various materials surrounding the copper metallization. It is found that by reducing the stress free temperature, electromigration lifetime can be improved. In order to explain the life-time behavior, an atomic flux divergence based coupled field finite element model is developed. The model predicts a reduction in the atomic flux divergence at the electromigration test condition due to the reduction in the stress free temperature as the key factor responsible for longer electromigration life-time observed experimentally.