Improved electrical and reliability performance of 65 nm interconnects with new barrier integration schemes

Abstract

Ta (N)/Ta bi-layer is a commonly used barrier in damascene copper interconnects for 90 nm and 65 nm technology nodes. A new barrier integration scheme so-called punch-through is currently used for 65 nm node. The main feature of the new deposition scheme is to introduce an etch-back step between the Ta (N) layer deposition and the Ta layer deposition. This intermediate etch step cleans up the bottom of via and also partially etch the underlying copper line with a depth of few nanometers. This step changes dramatically the bottom of via shape leading to via anchoring into the underlying copper line. In this paper we compare punch-through versus no punch-through approach. We show that the punch-through leads to a lower via resistance and to a tighter via resistance distribution, while keeping line resistance similar. We show that via anchoring into the underlying copper line coupled with a better tantalum step coverage dramatically reduces stress migration effect and also improves electro-migration performances at 65 nm technology node.