A copper-dielectric cap interface with high resistance to electromigration for high performance semiconductor devices

Abstract

In highly integrated semiconductor devices the time to failure of copper interconnects strongly depends on the properties of the copper-dielectric cap interface. In this work a production capable preparation of copper-dielectric cap interfaces with a high resistance to electromigration (EM) has been developed for 90 and 65 nm dual damascene technologies. With a new soft silicidation pretreatment of the copper metallization followed by a deposition of a SiCN or SiN cap the EM lifetime could be improved 3.5× referring to a standard SiCN capping process. The new pretreatment enables the formation of an epitaxial copper silicide layer on top of the copper metal lines which is seen as the key factor of the lifetime improvement. The new kind of cap layer process enables the lifetime improvement with only negligible increase of metal sheet resistance. The surface damage of copper and the low k inter-level dielectric which is typically caused during the copper precleaning could be minimized significantly. It is shown that there is no linear correlation between adhesion to copper and electromigration performance.