Electromigration Performance Research Articles

Application of Cu Reflow Process on Ru Liner for Advanced Nanoscale Interconnects

Abstract A novel physical vapor deposition (PVD) Cu reflow process with chemical vapor deposition (CVD) Ru liner was optimized for 10 nm generation interconnects and beyond. For these and future device generations, void-free Cu interconnects are a key requirement, and the PVD Cu reflow process improvements reported here provide significant advancement in enabling excellent Cu reflow performance. The Ru liner exhibited much better Cu reflow performance than a Ta liner by effectively suppressing Cu agglomeration during the Cu reflow process, likely due to a better adhesion to Cu. Reflow temperature and Ru thickness (continuity) are critical parameters for achieving good Cu reflow performance, and this optimized Cu reflow process with Ru liner did not show line top voids or sidewall voids, which are the two major void types often observed at this dimension when pursuing Cu fill with the conventional Cu seed and Cu plating fill scheme. Furthermore, this novel Cu reflow process exhibited an electromigration (EM) performance enhancement due to having better Cu fill quality.

Understanding electromigration failure behaviors of narrow cobalt lines and the mechanism of reliability enhancement for extremely dilute alloying of manganese oxide

Self-forming barriers for copper (Cu) interconnect metallization are well developed. However, the self-forming-barrier process and associated electromigration behaviors of narrow lines of cobalt (Co), a new interconnect wiring material for sub-10-nm semiconductor device nodes, are yet to be explored. In this study, we present an all-wet electroless trench-filling process to fabricate narrow (100 nm) lines of Co and MnO-added Co [Co(MnO)], then thermally annealed to some extent (400 °C/30 min) prior to electromigration testing. Empirical data obtained from accelerated electromigration testing, including failure lifetimes, current-density scaling factors, activation energies and physical failure profiles, consistently show that electromigration reliability of the Co lines is markedly enhanced by 0.1% added MnO. Transmission electron microscopy and focused ion beam imaging, along with dynamic adhesion strength data, reveal that the enhancement is related to annealing-induced segregation and dispersion of MnO particles at the interface with SiO2, ensuring adhesion of Co on SiO2, preventing interfacial interdiffusion and stuffing electromigration pathways. The adhesion strength, microstructures and Joule-heating data of Co and Co(MnO) are provided for the discussion of the differences in their electromigration performance and failure mechanism. Comments on electroless-plated Co as a new interconnect material are also given.

Electromigration Risk Assessment and Circuit Optimization using Innovative Multiphysics Modeling

With smaller and denser transistors, the physical flow of electrons may inhibit the performance of the device over time by forming voids and cracks at interconnects due to Electro-Migration (EM). Circuit designs that fail to meet EM specifications may lead to catastrophic failures and SI/PI performance degradation. One way of mitigating EM is to use multiple vias between layers of copper traces to reduce the current crowding effect. However, the quantities of vias may affect the current density and current redistribution inside critical joints. Current studies mainly focus on predicting the EM time-to-failure (TTF) based on the empirical Black’s equation. However, this method may not give enough insights about void formation and crack propagation and reflects the current redistribution that could impact the TTF. In this study, we compared the EM lifetime of Ball Grid Array (BGA) test vehicles with different structural designs and developed a methodology to consider the diffusion of atoms in solder joints based on Multiphysics field migration to study the current redistribution influence of vias. Moreover, crack propagation was also simulated to understand the failure mechanism. BGA traces without vias and with 8 vias are stressed under 5A, 7A, and 9A at 150C to compare the EM performance. Moreover, each test structure is manufactured with two different surface finishes: A and B. Based on the experimental results, Finite Element Analysis (FEA) simulations based on Atom Flux Divergence (AFD) were performed to compare with the experiment results. It was found that the current crowding effect could be significantly reduced by 8 vias compared to daisy chained traces. The study shows better EM resistance with 8 and 4 vias than no-via traces and helps predict the EM life of different structures to provide guidance for design optimization

Electromigration Reliability of Barrierless Ruthenium and Molybdenum for Sub-10 nm Interconnection

Cu interconnects suffer from increased resistance and poor reliability at a sub-10 nm width. Ru and Mo have been highlighted recently as the next interconnection material candidate due to their various advantages over Cu; they have lower resistance than Cu at sub-10 nm, do not diffuse into SiO2, and are etchable. Here, we evaluated the electromigration (EM) reliability of Ru and Mo to confirm their feasibility for the next-generation interconnection. The activation energy for EM failure is calculated by measuring the mean time to failure (MTTF) of film and wire structures while factoring in temperature increases with thermal coefficient of resistance (TCR) measurements. In addition, we investigate the EM properties in terms of resistivity-increasing parameters that originate from geometry and additional fabrication processes. Furthermore, we evaluate the EM performance in terms of electrochemical potential. Our findings confirm the feasibility of Ru as a promising candidate for next-generation interconnection applications, providing enhanced reliability compared to conventional Cu interconnects.

Electromigration failure in inkjet-printed Ag conductive lines

Electromigration (EM) is crucial to the reliability of most conductive lines used in electronics. In the present study, the EM characteristics of inkjet-printed Ag conductive lines were analyzed under various EM acceleration conditions to comprehend the EM failure behaviors associated with inkjet-printed Ag lines with nanoparticle inks. The evolution of the porosity level in the microstructure of the inkjet-printed Ag lines during the EM test was investigated to locate the EM failure positions in the line and identify the main driving force for EM mass transport. Two theoretical models (resistometric and Black’s) were employed to analyze the activation energy and expected lifetime of inkjet-printed Ag lines. This study indicates that the EM of Ag cations is directed toward the cathode by the direct force resulting from the electric field–ion interaction, resulting in EM failure near the anode and hillock formation near the cathode of the inkjet-printed Ag lines. The activation energy computed from the theoretical models suggests that the surface diffusion of Ag through the inkjet-printed line plays an important part in the EM failure mechanism. This research was a pioneering attempt to experimentally investigate the EM performance of inkjet-printed Ag lines.

Anaerobic swine digestate valorization via energy-efficient electrodialysis for nutrient recovery and water reclamation

The development of cost-effective and energy-efficient technologies to recover nutrients from digestate is important. Anaerobic digestate can be concentrated into bio-nutrient products through an electrodialysis (ED) process in an energy-efficient manner. Despite recent advances, the operation modes of ED for nutrient recovery from swine digestate are yet to be systematically evaluated from the perspective of energy-water efficiencies, and the determination of optimal operations in ED units is still ambiguous. In this study, two different operating modes of electrodialysis, i.e., constant voltage and constant current, are designed to evaluate the energy efficiency and effectiveness of nutrient recovery from anaerobic swine digestate. The ion removal ratio and current efficiency of the different modes and their associated electromigration performance (e.g., rate constants) are evaluated. The results indicate that the maximum removal efficiency (in terms of electrical conductivity) is 92.8% at a cell voltage of 2.4 V/cell using the constant voltage operation. The current efficiencies of NH4+ (43‒65%) are higher than that of other ions, such as K+ (12‒19%), Cl- (4‒7%), and PO43- (0.1‒1.5%). For nitrogen recovery, the required energy consumption was about 0.24‒15.2 kWh/kg-N (0.86‒54.7 kJ/g-N), corresponding to a removal ratio of ammonium from 70.8% to 99.1%. Based on the experimental data, the optimal operating conditions are identified using response surface models by considering process energy consumption and productivity to deliver energy-efficient nutrient separation. One candidate of the ideal conditions to achieve the total ion removal of ∼93% should be operated at a constant cell voltage of 1.15 V, corresponding to a productivity of 5.24 gal/hr/m2 at an energy consumption of 0.44 kWh/m3. Last, a conceptual design of cascading separation processes is proposed for digestate valorization as biofertilizers, nutrients, organic acids, and reclaimed water. A preliminary benefit-cost evaluation is then performed to evaluate the engineering and economic performance of the developed process for nutrient recovery from swine digestate. This article provides insight into practical large-scale applications of digestate valorization through energy-efficient separation, thereby realizing a circular economy system and a decarbonizing supply chain of bio-nutrients.

Electromigration Performance Improvement of Metal Heaters for Si Photonic Ring Modulators

Ring-based, resonant Si photonic (SiPho) devices are temperature sensitive and require thermal tuning for stable operation, which is accomplished with integrated metallic heaters. This paper investigates the combined electromigration (EM) and thermal performance of tungsten (W) heaters using calibrated electro-thermal finite element models. The current injectors that are used to supply the current to the heater are a known weak spot for electromigration. The presented modelling study shows the conflicting design requirements for optimal thermal performance and optimal EM performance, which results in the need of a careful trade-off, supported by experimental reliability data. Based on modelling results, new device designs are proposed with significant performance increase. Lastly, a new methodology is introduced which allows to predict the lifetime of the W-heaters, given specific operating conditions such as ambient temperature and required phase shift.

CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration

Electromigration (EM) is crucial for interconnect reliability. This article introduces the implementation and application of CacheEM which targets SRAM cache memory aging due to EM. CacheEM is based on a comprehensive framework including five parts: 1) microprocessor emulation; 2) memory cell array activity extraction; 3) computation of currents in segments of long complex interconnect structures; 4) evaluation of the time-dependent hydrostatic stress and the resistance shift of interconnects; and 5) characterization of the EM lifetime distribution of interconnects in the cache memory. The first two steps (top-down) are implemented with gem5 and cache simulation, respectively. These simulators export the number of read and write operations for each cell of a cache memory in a microprocessor after running benchmarks. Then, based on the number of operations and the currents corresponding to each operation, CacheEM calculates the equivalent current distribution in each interconnect segment as the third step (bottom-up). The currents due to read and write operations are stored in models which have been pretrained with a regression algorithm. These models provide accurate predictions of the corresponding currents under various parameter settings, such as temperature, supply voltage, and gate length. Afterward, the samples of time-dependent hydrostatic stress and the resistance shift in each interconnect segment are computed while incorporating the variations of the effective activation energy and critical stress. The EM lifetime distribution of the cache memory is extracted using predefined threshold values. The impact of configuration parameters on EM reliability and performance of the SRAM cache is analyzed by comparing EM lifetime distributions.

(Invited) Selective Metal Deposition for Advanced Metallization Schemes

'Invited'Starting from critical dimensions below 10 nm, the continuation of CMOS scaling requires the Cu replacement as an IC interconnect material by a barrierless metal with lower resistivity and better electromigration performance than Cu, such as Co and Ru. In addition, narrow dimensions of interconnect features require implementation of bottom-up metal fill schemes to mitigate defects in metal structures. At the same time, significant technological improvements are required to mitigate the pattern overlays and litho-based edge placement errors when forming multilevel structures with a half-pitch at or below 10 nm. The transition from standard multiple litho-etch deposition schemes to bottom-up area-selective deposition (ASD) is a very promising way to enable self-alignment of multilevel structures. The approaches to achieve ASD can be classified in three categories: i) intrinsic selectivity, ii) selectivity enabled by passivation of the “non-growth area” and iii) selectivity enabled by activation of the “growth area”. Among selective deposition processes, electroless deposition (ELD) and atomic layer deposition (ALD) can be effectively used due to their chemical nature and surface sensitivity. This work explores all three categories of ASD approaches for BEOL technology application, utilizing the above listed techniques for Co and Ru deposition.Intrinsically selective metal deposition can be realized for very limited number of material combinations used in IC manufacturing. Part of this work focuses on various H-based plasma treatments, which allow forming appropriate surface functionalities enabling ASD. Among various material combinations, the focus was set on amorphous carbon (a-C) as “non-growth” surface and Si-based materials, such as SiCN, as “growth” surface. An interaction of various compounds of H-based plasma, namely: H ions and H radicals with a-C was investigated experimentally. In order to support experimental observations, molecular dynamic modeling of a-C interaction with H plasma was performed, which allowed to understand the mechanisms of a-C chemical modification by H ions and radicals. Effectivity of H plasma treatment on ALD selectivity was studied for the case of selective Ru ALD using (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru(0) (EBECHRu) precursor with O2 co-reactant. In addition, an initial study of Ru ASD integration into patterned structures of technological relevant dimensions was performed.Direct implementation of intrinsically selective processes into production is a rare case in microelectronic technology. In most of the cases, however, blocking layers can be used. This work explores self-assembled monolayers (SAMs) as blocking layers for ALD. Screening of various siloxane-SAM precursors was performed to study the impact of SAM’s functional group, length of alkyl chain and deposition conditions on surface density of SAM molecules and, specifically, passivation properties of SAM against Ru ALD. An additional study was performed in order to analyze modification of (3-trimethoxysilylpropyl)diethylenetriamine (DETA)-derived SAM under ALD conditions (250 °C and O2 co-reactant). In-situ XPS as well as molecular-dynamic modelling were employed to investigate the mechanisms of DETA modification. Lastly, a removal of DETA-derived SAM from Cu “growth area” selectively with respect to SiO2 “non-growth area” using acetic acid was investigated to mitigate defectivity.Further, surface functionalization by SAMs can also be used to form appropriate surface terminal groups for further attachment of a metal catalyst or metal seed, used in subsequent selective ELD deposition. ELD is based on redox reactions on the metal substrate; therefore, it can be used for intrinsically selective metal deposition on metal substrates or metal seeds. SAMs-enabled selectivity can be used for metal growth on a dielectric surface selectively with respect to another type of the dielectric material. In the case of ELD bottom-up growth in a trench, the metal catalyst should be selectively deposited at the trench bottom dielectric layer. In this work, the selectivity of Pd metal catalyst promoted by selective surface functionalization by SAMs was investigated. It has been shown that SAMs with amino functional groups form covalent bonds with Pd catalyst, which is commonly used as a seed for subsequent ELD of various metals including Co on the Pd seed. Since the electrical properties of interconnect material are of crucial importance, an additional study of ELD Co resistivity was performed, including in-depth analysis of Co recrystallization revealing Co grain size dependency on the film resistivity.In conclusion, area-selective metal deposition processes are an important part of future microelectronic technology. This work explores ASD of Ru and Co, as the most promising Cu replacement metals. For the deposition of these metals, surface sensitive techniques are used, namely ALD and ELD. For the cases, where intrinsic selectively of the deposition technique cannot be realized for the combination of materials used in the process flow, SAM-based passivation and SAM-based activation layers were investigated.

Gallium-Enhanced Aluminum and Copper Electromigration Performance for Flexible Electronics.

Wide range binary and ternary thin film combinatorial libraries mixing Al, Cu, and Ga were screened for identifying alloys with enhanced ability to withstand electromigration. Bidimensional test wires were obtained by lithographically patterning the substrates before simultaneous vacuum co-deposition from independent sources. Current–voltage measurement automation allowed for high throughput experimentation, revealing the maximum current density and voltage at the electrical failure threshold for each alloy. The grain boundary dynamic during electromigration is attributed to the resultant between the force corresponding to the electron flux density and the one corresponding to the atomic concentration gradient perpendicular to the current flow direction. The screening identifies Al-8 at. % Ga and Cu-5 at. % Ga for replacing pure Al or Cu connecting lines in high current/power electronics. Both alloys were deposited on polyethylene naphthalate (PEN) flexible substrates. The film adhesion to PEN is enhanced by alloying Al or Cu with Ga. Electrical testing demonstrated that Al-8 at. % Ga is more suitable for conducting lines in flexible electronics, showing an almost 50% increase in electromigration suppression when compared to pure Al. Moreover, Cu-5 at. % Ga showed superior properties as compared to pure Cu on both SiO2 and PEN substrates, where more than 100% increase in maximum current density was identified.

Electromigration Reliability of Advanced High-Density Fan-Out Packaging With Fine-Pitch 2-/2-μm L/S Cu Redistribution Lines

The novel fan-out (FO) packaging incorporating fine-pitch small linewidth Cu redistribution line (RDL) technology was designed for achieving high-density packaging. However, the downsizing of Cu RDLs gives rise to increasing current densities and raises the electromigration reliability concerns. The failure mechanism involved under electromigration in the advanced fine-pitch package still remains unclear at the present stage. This article investigated the electromigration reliability and the failure mechanism of an advanced FO packaging with fine-pitch 2-/2- $\mu \text{m}$ line/spacing Cu RDLs, $3~\mu \text{m}$ in thickness and 20 or $600~\mu \text{m}$ in length, embedded in polyimide dielectric layers. The Cu RDLs were stressed with the electric current at $8.8\times 10^{5}$ A/cm2 under an ambient 180 °C. The geometry effects of the Cu RDL on the electromigration performance were also elaborated, and the design rule was proposed for reliability optimization. The Cu RDL incorporating a bent-line (45°) structure was found to exhibit a better electromigration resistance compared with the one incorporating a straight-line structure. The in situ resistance analysis revealed a steady resistance increase followed by a rapid resistance jump until open-circuit failure for both 20- and 600- $\mu \text{m}$ -long Cu RDLs. The fracture microstructures further revealed the failure occurrence in the middle region of the Cu RDL rather than on the cathode side, showing atypical failure mechanism under electromigration. The local heat accumulation in the middle region of the Cu RDL produced a large thermal gradient and further triggered Cu thermomigration, which were responsible for the electromigration-induced failure in the fine-pitch Cu RDLs.

(Invited) Alternative Metals for Beyond-Cu Interconnects

In recent technology nodes, interconnect scaling has become a major bottleneck for the reduction of the area of CMOS circuits. In the near future, interconnect dimensions will reach 10 nm and below. Reducing the cross-sectional area of interconnect wires and vias increases their resistance and consequently degrades the performance of the circuit. This geometrical effect is aggravated by an increased resistivity of the conductor metal, Cu, due to enhanced surface and grain boundary scattering. Moreover, it becomes increasingly difficult to ensure the reliability of scaled Cu interconnects. Barrier layers, such as TaN, are required to limit diffusion into the surrounding dielectrics. Resistance to electromigration is reduced in small dimensions, which can be mitigated e.g. by Co liners. However, both barriers and liners reduce the volume available for Cu while contributing little to the line conductance.These issues have recently led to an increased research for alternatives to the current Cu dual damascene interconnect technology. Materials innovation is a key to mitigate the reduction of interconnect performance. An ideal conductor metal allows for reliable interconnect operation without requiring barrier or liner layers, thus maximizing the available conductor volume. Moreover, it possesses a lower sensitivity to surface and grain boundary scattering than Cu, which means that the resistivity degrades more gradually with reduced interconnect line width. This property can be linked to a smaller mean free path of the charge carriers with respect to Cu (~40 nm) and thus metals with short mean free paths have been of particular interest.To identify suitable alternative conductor metals, we have developed a staged approach, which is schematically represented in the figure. Ab initio calculations of the product of the bulk resistivity and the mean free path as a figure of merit [1,2] are used to shortlist potential candidate metals. While a short mean free path indicates a weak sensitivity to finite size effects of the resistivity due to enhanced surface and grain boundary scattering, a low bulk resistivity is of equal importance to ensure a low resistivity at small dimension. By contrast, the cohesive energy (or the melting point) of a metal can be used as proxies for its expected electromigration performance and the need for barrier layers. This approach has now been applied to all relevant elemental metals as well as many binary and some ternary intermetallics. As concerns elemental metals, Co, Mo, as well as the Pt-group metals show particularly promising behavior. We will also review the situation for binary and ternary intermetallics.In a next step, thin film experiments have been used to assess the performance of the shortlisted metals experimentally. We will show that in particular several Pt-group metals show lower resistivities than Cu for ultrathin films with thicknesses below 10 nm. In addition, opportunities and challenges of binary or ternary intermetallics with respect to elemental metals will be discussed. In a third step, scaled interconnect wires of different alternative metals have been fabricated using a metal spacer process based on ion-beam etching [3-5]. The results indicate that Co, Ru, Ir, and Rh show promise to outperform Cu in narrow dimensions. Calibrated compact models of the line resistance indicate that the main gain in resistance over Cu interconnect lines and vias stems from the increased conductor volume since no barrier and line layers are required for reliable operation with a smaller contribution of the reduced resistivity. Finally, the remaining challenges in the integration of alternative metals in scaled interconnects are discussed.[1] D. Gall, J. Appl. Phys. 119, 085101 (2016).[2] S. Dutta, K. Sankaran, K. Moors, G. Pourtois, S. Van Elshocht, J. Bömmels, W. Vandervorst, Z. Tőkei, and C. Adelmann, J. Appl. Phys. 122, 025107 (2017).[3] L.G. Wen, et al., ACS Appl. Mater. Interfaces 8, 26119 (2016).[4] S. Dutta, S. Kundu, A. Gupta, G. Jamieson, J.F. Gomez Granados, J. Bömmels, C.J. Wilson, Z. Tőkei, and C. Adelmann, IEEE Electron Dev. Lett. 38, 949 (2017). Figure 1

Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview

Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so that the entire surface of the chip can be covered with bumps for the highest possible input/output (I/O) counts. The present article reviews the manufacturing processes for the fabrication of flip-chip bumps for chip–package interconnection. Various solder bumping technologies used in high-volume production include evaporation, solder paste screening and electroplating. Evaporation process produces highly reliable bumps, but it is extremely expensive and is limited to lead or lead-rich solders. Solder paste screening is cost-effective, but issues related to excessive void formation limits the process to low-end products. On the other hand, electrochemical fabrication of flip-chip bumps is an extremely selective and efficient process, which is extendible to finer pitch, larger wafers and a variety of solder compositions, including lead-free alloys. Electrochemically fabricated copper pillar bumps offer fine pitch capabilities with excellent electromigration performance. Due to these virtues, the copper pillar bumping technology is emerging as a lead-free bumping technology option for high-performance electronic packaging.

On the design of an automated system for the characterization of the electromigration performance of advanced interconnects by means of low-frequency noise measurements

On the design of an automated system for the characterization of the electromigration performance of advanced interconnects by means of low-frequency noise measurements

Effect of Parametric Variations on Electromigration in Integrated Circuits

This research paper focuses on the effects of electromigration in integrated circuits at the nanoscale domain. This is an investigative work that shows how various process and parametric variation effects on electromigration. With integrated circuits reaching in the nanoscale domain, electromigration is becoming more of a prominent problem. Being able to find changes into the integrated circuits to provide a better electromigration performance is crucial for future emerging nanotechnologies. Therefore, this paper will go through previous research work to show the evolution of Black’s equation and see if Black’s equation could use on nanoscale integrated circuits. Also, it will be showing future iterations of the equation and comparing them with constant variables. Besides, a comparison of aluminum and copper interconnects and how electro migration happens differently are also discussing in this paper. Then a conclusion on how Black’s equation could use with nanoscale technologies to predict the time during the occurrence of electro migration.

Process Optimization for Electron Down-Flow Electromigration Improvement in Copper Interconnects

Due to asymmetric structure of Copper (Cu) interconnects, Cu electromigration (EM) is related to the electron flow direction. In various technological nodes, Cu EM performance with electron down-flow direction is generally worse than that with electron up-flow direction due to the presence of voiding underneath the via. This study investigates Cu EM behavior with electron down-flow. The failure modes were verified and optimized processes were provided to improve EM performance. Additionally, layout geometry effect on electron down-flow EM was discussed.

Mathematical model of segmented capillary electromigration performances depending on stationary phase physicochemical properties

Segmented capillaries comprising two segments with different surface charges of polymer layers are prepared. One segment with a neutral surface charge is responsible for separation and another one with negatively charged surface provides the electro-osmotic flow adjustment. The average electro-osmotic flow rate is found to correlate with the length of negatively charged segment. A mathematical model is suggested to describe electromigration performances of segmented capillaries depending on the segments length ratio also taking into account the stationary phase/coating with definite surface properties (ξ—potential) or electroosmotic flow rate.

Resistance Decay of Cu/Porous Low- ${k}$ Interconnect: Modeling and its Impact on Electromigration

It was found previously the resistance of Cu interconnect ( ${R}$ ) could decrease during baking and acceleration test, owing to moisture invasion through the nanoporous low- ${k}$ followed by moisture-induced oxidation of Ta-based liner and specularity recovery of the electron scattering at Cu/Ta interface. In this paper, a model is established to quantitatively interpret the underlying kinetics. It is shown that the model fits well with the experimentally observed hump-shaped temperature dependence of the R decay rate of Cu/porous SiCOH interconnects at 28-nm node at 170 °C~350°C. It reveals that the liner oxidation and resistance decay are controlled mainly by the migration of metal cation through the as-oxidized liner at the low temperatures but by the desorption/diffusion of the chemisorbed moisture in the low- ${k}$ at the high temperatures. Particularly, the model well reproduces the modest and unexpectedly significant low- ${k}$ -thickness dependence of the decay rate at the low and high temperatures, respectively, which indicates clearly the temperature-dependent influence of the tortuous diffusion path of moisture in the porous low- ${k}$ . The intimate relationship of Cu electromigration performance to such ${R}$ decay is also demonstrated.

Accelerated Metastable Solid–liquid Interdiffusion Bonding with High Thermal Stability and Power Handling

Emerging high-performance systems are driving the need for advanced packaging solutions such as 3-D integrated circuits (ICs) and 2.5-D system integration with increasing performance and reliability requirements for off-chip interconnections. Solid–liquid interdiffusion (SLID) bonding resulting in all-intermetallic joints has been proposed to extend the applicability of solders, but faces fundamental and manufacturing challenges hindering its wide adoption. This paper introduces a Cu-Sn SLID interconnection technology, aiming at stabilization of the microstructure in the Cu6Sn5 metastable phase rather than the usual stable Cu3Sn phase. This enables formation of a void-free interface yielding higher mechanical strength than standard SLID bonding, as well as significantly reducing the transition time. The metastable SLID technology retains the benefits of standard SLID with superior I/O pitch scalability, thermal stability and current handling capability, while advancing assembly manufacturability. In the proposed concept, the interfacial reaction is controlled by introducing Ni(P) diffusion barrier layers, designed to effectively isolate the metastable Cu6Sn5 phase preventing any further transformation. Theoretical diffusion and kinetic models were applied to design the Ni–Cu–Sn interconnection stack to achieve the targeted joint composition. A daisy chain test vehicle was used to demonstrate this technology as a first proof of concept. Full transition to Cu6Sn5 was successfully achieved within a minute at 260°C as confirmed by scanning electron microscope (SEM) and x-ray energy dispersive spectroscopy (XEDS) analysis. The joint composition was stable through 10× reflow, with outstanding bond strength averaging 90 MPa. The metastable SLID interconnections also showed excellent electromigration performance, surviving 500 h of current stressing at 105 A/cm2 at 150°C.

Development of Advanced Cobalt CMP Slurry Platform By Electrochemical Screening and Polishing Studies

In advanced nodes at 10 nm and below, cobalt (Co) metal is under investigation to replace copper (Cu) in metal lines and vias in back end of line (BEOL) for the first few metal layers due to its better electromigration performance, lower resistivity, conformal coverage in high aspect ratio features, and overall improved device performance. These new integration schemes require Co chemical mechanical planarization (CMP) steps to achieve planarity and desired target thickness. However, Co metal is prone to corrosion in aqueous solutions and its lower redox potential makes it an easy galvanic corrosion target under CMP conditions. Commercial Cu bulk slurries are not compatible for Co polishing as they show significant corrosion defects such as pitting, rough surface, and missing lines after CMP. Advanced Co bulk CMP slurries, therefore, need to contain effective chelator, corrosion inhibitor, and additives at suitable slurry pH to eliminate corrosion defects, while still delivering high Co removal rates (2000 to 5000 Å/min). In this presentation, we will discuss the systematic approach taken to develop a Co bulk CMP slurry formulation platform that can provide high removal rates and low/no corrosion, through development of fundamental understanding of Co surface chemistry, chelation, and corrosion properties. Results and key learnings from the extensive screening techniques such as Tafel polarization, galvanic corrosion, static-etch corrosion, quartz crystal microbalance, and X-ray photo electron spectroscopy analyses used to identify the ideal slurry pH, effective chelators, and corrosion inhibitors will be shared. In addition, Co blanket and pattern wafer polishing performances will be presented for the leading slurry formulations.