Electroless Barrier Research Articles

(Invited) Film Properties of Various Electroless Plated Co Alloy Films Formed on SiO2/Si Substrate and Its Interdiffusion Properties Against Cu

There is a serious problem of poor side wall coverage for the sputtered barrier metals in high aspect ratio TSVs. We have proposed electroless plated Co-alloy barrier metals for TSV. For this purpose, we prepared various CoB and CoWB alloys with different atomic compositions and crystalline structures. Furthermore, we evaluated interdiffusion properties of Cu/Co-alloy/Si stacked structure by SIMS analysis. It turned out that the electroless CoWB film containing larger amount of W has excellent diffusion barrier property than other CoWB films with smaller W content. We formed electroless barrier films of CoB and CoWB using Pd nanoparticle catalyst on SiO2/Si substrate [1]. For evaluation of Cu interdiffusion properties by SIMS, we deposited Cu and TiN thin films successively by sputtering on the barrier film. The ratio of the atomic composition was changed by adjusting the ratio of cobalt sulfate, tungstic acid, and some other contents of the plating bath. SIMS depth profiles of CoB (Fig.1-a) and CoWB films after annealing at 400 ℃ (Fig.1-b) are shown in Fig.1. There was a large interdiffusion between Cu and CoB after 400 ℃ annealing (Fig.1-a). Co-Silicide formation significantly occurred and Si atoms diffused into CoB layer. However, interdiffusion was significantly suppressed in the case of Co-20%W-B film (Fig.1-b). These results suggest that W atoms existed in CoWB have a strong effect of suppressing Cu diffusion in Co film, and CoWB with 20 atom % W showed a good diffusion barrier property. The present study suggests that the electroless plated CoWB having a larger W content has a high potential as a diffusion barrier film for the via last TSV process.[1] F. Inoue, T.Shimizu, F.Miyake, R.Arima, T.Ito, H.Seki, Y.Shinozaki, T.Yamamto, and S.Shingubara, Microelectronic Engineering, 106 (2013) 164–167.[2] T. Iseri, S.Shindo, Y.Miyachi, A.Hirate, S.Tanaka, T.Shimizu, T.Ito, S.Shingubara, Jpn. J. Appl. Phys. 57 (2018), 07MB02-1~6. Figure 1

Electroless Plating of Diffusion Barrier Films on SiO2 and Evaluation of Film Characteristics

For fabrication of through-silicon via (TSV) of 3-D integration, sputtering or ALD are used for the barrier and seed layers formation, however, high cost processes using high vacuum instruments have hindered wide application of 3-D integration technologies. We have studied formation of barrier and seed layers with electroless plating which enables significant reduction of fabrication cost [1, 2]. Use of Pd nanoparticle catalyst adsorbed on silane coupling agent at TSV sidewall [3] is very effective for a highly conformal film deposition in the high aspect ratio TSV holes. In this study, we formed electroless barrier films such as CoWP and NiWP on SiO2 at various bath conditions. We evaluated film characteristics such as electrical resistivity, crystalline structure, adhesion property, alloy composition, Cu diffusion barrier properties, etc.Figure 1 shows SEM cross-sectional images of the barrier films and XRD profiles before and after annealing (400 oC, 30min. in vacuum).The crystalline structure of the as deposited CoWP film was amorphous and it remained almost amorphous after heat-treatment. On the other hand, the crystal structure of the as deposited NiWP film was also amorphous, but several peaks of NiP alloy appeared after heat-treatment and it turned to poly crystal film. In addition, we formed Cu seed layer on the barrier metal by displacement plating and studied Cu inter- diffusion properties after annealing. Reference [1] F. Inoue, T. Shimizu, H. Miyake, R. Arima,T. Ito, H.Seki,Y. Shinozaki, T. Yamamoto, and S.Shingubara, Microelectronic Engineering, 106(2013) 164–167. [2] F.Inoue, T.Shimizu, T. Yokoyama, H. Miyake, K. Kondo, T. Saito, T. Hayashi, S. Tanaka, T. Terui and S. Shingubara, Electrochimica Acta, 56-17 ,6245-6250, (2011). [3]W. J. Dressick, C. D. Dukey, J. H. Georger. Jr, G. S. Carabrese, and J. M. Calvert, J Electrochem. Soc., 141 (1) 210 (1994) Figure 1

(Invited) All-Wet TSV Fabrication Using Electroless Plated Barrier and Cu Seed Layers with Pd Nanoparticle Catalyst

Fabrication of TSV is one of key technologies for 3D-ICs. Filling of Cu electrode materials in a small dimension of TSV is essential for realizing fine-pitch TSVs, which reduce the lisk of thermal stress concentration issues. Cost reduction is also required to be feasible TSVs for a variety of devices. All-wet fabrication of TSVs using electroless plating of barrier and seed is one of solutions to fullfill these requirements. For realizing conformal thin barrier metal layers of Co-alloy or Ni-alloy electroless barriers in a high aspect TSV, Pd nanoparticles as catalyst are very effective because their adsorption is uniform throughout top to bottom of TSV. Furthermore they shows improvements of adhesion between dielectric and metal [1,2]. Adhesion issue is a serious obstacle for electroless plated films in general, however, we found displacement plating of Cu on electroless plated barrier layer has an excellent adhesion property. Finally, we succeeded in formation of a high aspect ratio TSV with superfilled Cu on electroless barrier/seed layers. Reliability aspects relating interdiffusion of Cu against the barrier layers will be discussed further. [1] F.Inoue, T.Shimizu, T. Yokoyama, H. Miyake, T.Ito, H. Seki, Y.Shinozaki, T.Yamamoto,and S.Shingubara, Electrochimica Acta, 82, 372-377 (2012). [2] F. Inoue, T. Shimizu, H. Miyake, R. Arima, T. Ito, H. Seki, Y. Shinozaki, T. Yamamoto,S.shingubara, Microelectronic Engineering, 106, 164-167 (2013).

Reliability tests of electroless barriers against copper diffusion under bias-temperature stress with n- and p-type substrates

To investigate the similarity and difference of substrate conduction type in the time-dependent dielectric breakdown (TDDB) tests for the barrier integrity against Cu diffusion under bias-temperature stress (BTS), the TDDB reliability of electroless NiB and CoWP/NiB was determined by metal oxide semiconductor (MOS) structures on n-type Si (n-Si) substrates, and the test results were compared with those using p-type Si (p-Si) substrates. The TDDB results and mechanism were observed to be qualitatively the same as Cu diffusion for both conduction types. However, the TDDB lifetime using p-Si was found to be potentially shorter because of the reverse bias conditions than that using n-Si under the forward bias conditions.

Manufacturing technology of intra- and interchip interconnects for modern ULSIs: Review and concepts of development

Technological operations involved in manufacturing multilevel ULSI interconnections by the dual damascene (DD) method have been analyzed. Problem issues are considered, including (i) etching of porous intralevel insulation with ultralow values of dielectric constant, (ii) application of metal barrier and seed layers onto the porous surface of etched dielectric spacers, in which copper conductors have to be formed, (iii) low mechanical strength of porous dielectric spacers between copper conductors, (iv) insufficient stability of copper conductors with respect to failures as a result of electromigration, and (v) rapid growth in the resistivity of copper conductors with decreasing width, and limited possibility of compensating this factor by increasing conductor height (thickness). Possible approaches to solving these problems are proposed. According to one of these, horizontal copper conductors are formed first and then a porous dielectric is incorporated into the gaps between conductors by the method of chemical sol-gel deposition from solution by spin-on-dielectric (SOD) method on a centrifuge. The horizontal conductors can then be formed by the standard single-damascene process of copper deposition into temporal mask that is subsequently removed and replaced by the porous dielectric. According to another method, copper conductors are formed by local electrochemical deposition on the wafer surface that is preliminary covered by the barrier layer (BL), seed layer (SL), and a temporal mask, in which a pattern of conductors is prepared by etching down to the SL surface. In this case, the deposited copper conductors initially possess a textured crystalline structure, which facilitates the formation of elongated crystallites during subsequent thermal recrystallization. The surface of conductors can be also covered by local electrochemical process with an electroless barrier layer (e.g., of CoWP). Then, the BL and SL are removed and a porous ultralow-dielectric-constant insulator is incorporated into the gaps between copper conductors. The next stage of forming interconnections in multicrystal ULSIs consists of a three-dimensional (3D) vertical assembly of thinned chips by connecting them with copper conductors formed using through substrate via (TSV) technology. In order to improve heat removal from the assembly and increase its mechanical strength, the filling of vertical through channels in chips by copper is supplemented by copper plating of side edges and the formation of microbumps on crystal surfaces.

Cu Displacement Plating on Electroless Plated CoWB Layer on SiO2 and Its Adhesion Property

For realizing high aspect ratio TSV with a low cost, the all-wet process utilizing electroless barrier and Cu-seed layers prior to Cu electroplated fill is one of the most promising methods. However, improvement of adhesion property of electroless plated barrier and seed layers on SiO2 has been intensively required. In this study, we studied displacement plating of Cu on electroless CoWB layer formed on SiO2 in an acidic bath. It turned out that displacement-plated Cu film grew with sacrifice of the partial CoWB layer, and showed a high adhesion strength that was enough to pass CMP process.

Electroless Nickel Alloy Deposition on SiO<SUB>2</SUB> for Application as a Diffusion Barrier and Seed Layer in 3D Copper Interconnect Technology

Electroless Ni-P films were investigated with the aim of application as barrier and seed layers in 3D interconnect technology. Different shapes of blind-via holes were fabricated with a deep reactive ion etcher and SiO2 formed on these holes as an insulating layer. The surface of the substrate has been made hydrophilic by O2 plasma treatment with 100 W of power for 20 min. Electroless Ni-P films were deposited as both a diffusion barrier and a seed layer for Cu filling process. Prior to plating, substrates were activated in a palladium chloride solution after sensitization in a tin chloride solution with various conditions in order to deposit uniform films in TSV. After the formation of the electroless barrier layer, electro Cu was plated directly on the barrier layer. Ni-P films fabricated in blind-via holes were observed by scanning electron microscope. Energy dispersive spectroscopy line scanning was carried out for evaluating the diffusion barrier properties of the Ni-P films. The electroless Ni-P layer worked well as a Cu diffusion barrier until 300 degrees C. However, Cu ions diffused into barrier layer when the annealing temperature increases over 400 degrees C.

Low Cost, Scalable and Selective Electrochemical TSV Fill Technology for 3D IC Interconnects

Physical and economical limitations for 2D scaling (so called “Moore’s Law”) prevents further increase of integration density to improve the performance of integrated circuits (IC). These challenges have stimulated the development of 3D through-silicon via (TSV) technology (so called “More than Moore”) in order to increase the speed and the bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the implementation of 3D TSV technology is limited by the high cost of 3D TSV fill (due to the use of expensive vapor deposition and chemical-mechanical processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high TSV aspect ratios and smaller via sizes (to increase I/O). The objective of this investigation is to address the cost and scalability issues in order to enable cost-effective and reliable fill of high aspect ratio 3D TSVs. In this paper, we will review the low temperature and scalable process technology for 3D TSV fill employing the selective electrochemical through-via metal (Ni alloy/Cu or Co alloy/Cu) filling technology which is more economical because it will eliminate expensive chemical-mechanical polishing (CMP) process and replace expensive plasma-enhanced chemical vapor deposition (PE CVD) and physical vapor deposition (PVD) processes with low cost, lower temperature (<100 oC), more scalable (AR > 30:1) selective electrochemical process (LoCoSS process). LoCoSS process technology includes the following major electrochemical process steps: anodic oxidation to form isolation layer, selective electroless barrier deposition and selective electrochemical fill that can be implemented using one LoCoSS electrochemical processing tool instead of four POR processing tools utilizing different technologies – PE CVD isolation, PVD barrier/seed, Electrofill and CMP.The activation of thin continuous electroless barrier films (Ni or Co alloys) with high adhesion on the isolation surface (SiO2) is challenging. To overcome this technical risk, a novel nanoactivation process has been developed with the use of self-assembled monolayers [Si-(CH2)x-NH2-OH] and catalytic functionalized nanoparticles (Pd/Cu). To increase the adhesion of the deposited barrier films, the covalent bonding between substrate and the SAM binding layer has been engineered through the proper choice of the functional groups. Selective activation has been achieved through the mechanical removal of catalysts from the front surface (except inside the TSV’s) and the use of photosensitive TiO2/catalyst process. Besides, robust and defect-free fill of high aspect ratio TSV’s requires the development of electroless Cu superfill process with the use of suppressing additives in the plating solution such as high molecular weight polyacrylic acid (PAA) and polyethylene glycols (PEG). Selective electroless Cu plating into high aspect ratio TSV was successfully demonstrated with complete coverage of electroless barrier layer and low overplating on the field. Copper electroplating from NANO3D suppression-based plating solutions was also used to enable high speed and uniform plating of flat Cu bumps that can be used to interconnect chips in 3D microelectronics systems. LoCoSS technology could accelerate the mass-scale adoption of low cost and scalable TSV technology in semiconductor manufacturing. Implementation of our proprietary LoCoSS process will lower the cost of 3D ICs with the potential to reduce the cost by over 2X and increase scalability by over 3X for volume production. Besides, enabling low cost 3D ICs with our technology will allow heterogeneous system generation for next generation smart phones and other communication devices as well as increase of the bandwidth, memory capacity and decrease of the signal transmission delay within computing chips.

Improvement of Adhesion Strength of Electroless Barrier Layer and Its Application to TSV Process

The all-wet process for TSV-fill utilizing electroless barrier and seed technologies prior to electroplating of Cu is promising methods to realize low-cost and highly reliable Cu-filled TSVs for 3-D integration of Si. Although there have been numerous studies to form electroless barrier layers such as Co- and Ni- alloys, poor adhesion of these barrier layers have been a serious problem. In this study, we studied effect of various additives on the adhesion strength of electroplated CoWB film. It is shown that addition of saccharine, which has both sulfone- and amino- groups, significantly improved adhesion strength.

Control of Adhesion Strength and TSV Filling Morphology of Electroless Barrier Layer

In this study, we investigated to control adhesion property of the electroless plated barrier layer on SiO2 by addition of saccharin and its deposition profile in a high aspect ratio TSV with inhibitor and saccharin. We achieved high adhesion strength of barrier layer by addition of suitable amount saccharin. Furthermore, we succeeded in the formation of thin continuous electroless barrier layer for a high aspect ratio TSV with addition of both inhibitor and saccharin. The proposed highly adhesive and conformal electroless barrier layer formation would provide a highly reliable all-wet TSV filling process.

Control of Adhesion Strength and TSV Filling Morphology of Electroless Barrier Layer

not Available.

Barrier Integrity of Electroless Diffusion Barriers and Organosilane Monolayer against Copper Diffusion under Bias Temperature Stress

Barrier integrity of electroless NiB and CoWP/NiB thin layers against copper (Cu) diffusion was evaluated by time-dependent dielectric breakdown (TDDB) under bias temperature stress (BTS) using metal oxide semiconductor (MOS) test structures. The BTS tests were carried out also for an approximately 2.2-nm-thick organosilane monolayer (OSML), which has been used as the underlayer of the electroless barrier layers (EBLs). It was found that the barrier integrity of the EBLs was NiB 40 nm > NiB 10 nm > CoWP/NiB 40 nm = CoWP/NiB 10 nm in this order. The field acceleration parameter of the TDDB lifetime was almost the same for all EBLs. Initial failures and wide lifetime distributions were observed for CoWP/NiB when the NiB catalyst layer for CoWP was not thick enough, which is considered to be due to the large surface roughness. In addition, the OSML was found to have some barrier properties. Although the reliability of OSML was inferior to electroless NiB and CoWP/NiB barrier layers, it is considered that the barrier integrity of the EBLs was partially supported by the OSML.

Barrier Integrity of Electroless Diffusion Barriers and Organosilane Monolayer against Copper Diffusion under Bias Temperature Stress

Barrier integrity of electroless NiB and CoWP/NiB thin layers against copper (Cu) diffusion was evaluated by time-dependent dielectric breakdown (TDDB) under bias temperature stress (BTS) using metal oxide semiconductor (MOS) test structures. The BTS tests were carried out also for an approximately 2.2-nm-thick organosilane monolayer (OSML), which has been used as the underlayer of the electroless barrier layers (EBLs). It was found that the barrier integrity of the EBLs was NiB 40 nm > NiB 10 nm > CoWP/NiB 40 nm = CoWP/NiB 10 nm in this order. The field acceleration parameter of the TDDB lifetime was almost the same for all EBLs. Initial failures and wide lifetime distributions were observed for CoWP/NiB when the NiB catalyst layer for CoWP was not thick enough, which is considered to be due to the large surface roughness. In addition, the OSML was found to have some barrier properties. Although the reliability of OSML was inferior to electroless NiB and CoWP/NiB barrier layers, it is considered that the barrier integrity of the EBLs was partially supported by the OSML.

Electroless Barrier Deposition with Pd Nanoparticle Catalyst in High Aspect Ratio TSV

not Available.

Formation of electroless barrier and seed layers in a high aspect ratio through-Si vias using Au nanoparticle catalyst for all-wet Cu filling technology

An all-wet process was achieved using electroless deposition of barrier and Cu seed layers for fabrication of a high aspect ratio through-Si via (TSV). Formation of a thin barrier metal layer of Ni–B, Co–B and Co–W–B is possible using a Au nanoparticle (AuNP) catalyst, which is densely adsorbed on the SiO 2 of the TSV sidewall. A silane coupling agent of 3-aminopropyl-triethoxysilane is effective for enhancement of the density of adsorption for AuNP. A conformal electroless Cu layer is deposited on the barrier layer by displacement plating without a catalyst. The adhesion strength between the electroless barrier layer and the SiO 2 substrate is increased by annealing at 300 °C. These results strongly suggest that an all-wet process for the formation of Cu-filled TSV with a high aspect ratio is practically possible.

Formation of Electroless Barrier Layer Using Au Nanoparticles Catalyst for All-Wet TSV-Fill Technology

not Available.

Electroless deposition of CoWP: Material characterization and process optimization on 300 mm wafers

The use of copper as a metal for interconnections has driven the apparition of new technological solutions. Selective barriers against copper diffusion deposited by electroless reaction bring interests in term of electromigration. In this article, CoWP electroless barriers deposited in a 300 mm Semitool Raider equipment are studied. Good uniformity for a standard thickness of 15 nm is demonstrated. Different growth rates of the barrier as a function of copper grain orientation are observed. The composition of the barrier is constant throughout the film. The deposition is selective, but corrosion phenomena and a superficial metallic contamination on the interline dielectric are revealed. The selectivity of the process is confirmed electrically for 12 nm thick barriers. The impact of copper corrosion on line resistance is addressed through preclean optimization.

Characterization of Ultrathin Electroless Barriers Grown by Self-Aligned Deposition on Silicon-Based Dielectric Films

A self-aligned, electrochemically integrated seeding/plating approach is developed for fabricating patterns of cobalt- (or nickel-) based metallic barriers and copper films selectively on silicon-based dielectric (hybrid siloxane-organic polymer and films using electroless plating. High-resolution X-ray absorption spectroscopy, transmission electron microscopy, atomic force microscopy, and grazing-incidence X-ray diffractometry indicate that, after they have been appropriately pretreated by a gaseous plasma or and basic aqueous solutions that contain sufficient amounts of peroxide hydrogen the dielectric films can adsorb highly populated metallic (nickel or cobalt) precipitates of sizes between 2 and 4 nm, which catalyze the deposition of ultrathin (⩽20 nm) barriers. The barriers are initially highly resistive and contain ultrafine (3-5 nm) crystallites embedded in amorphous-like, 20 nm grains, but become highly conductive (50-80 μΩ-cm) following optimal annealing at temperatures ⩾470°C because of crystallization, grain growth, and precipitation of Finally, the capacity of this method to fabricate “self-aligned” patterns of barrier and copper is established, and the adhesion strength and effectiveness of the barriers against copper’s diffusion/drift are quantified. The importance of the plasma pretreatment and the use of hydrogen peroxide (in the SC-1 solution) is also addressed. © 2004 The Electrochemical Society. All rights reserved.

Self-Aligned Deposition Process for Ultrathin Electroless Barriers and Copper Films on Low-k Dielectric Films

A self-aligned, integrated plating technique based on plasma physics and colloidal-related chemistry is proposed to fabricate patterns of ultrathin (≤20 nm) Co-based barriers and copper films in a selective manner on dielectric (HOSP and SiO 2 ) films using electroless plating. High-resolution X-ray absorption spectroscopy, transmission electron microscopy, and atomic force microscopy reveal that, once properly pretreated by a gaseous plasma (O 2 or H 2 /N 2 ) and hydrogen peroxide (H 2 O 2 ) in a basic aqueous solution, the dielectric films can adsorb highly populated metallic (Ni) precipitates of sizes approximately from 2 to 4 nm to catalyze the deposition of electroless Co-based barriers. Finally, the capability of this technique to fabricate self-aligned patterns of barrier and copper is demonstrated and the importance of the plasma pretreatment and hydrogen peroxide (in SC-1 solution) is discussed.

The electrical and material properties of MOS capacitors with electrolessly deposited integrated copper gate

The electrical properties of electroless-deposited barriers were studied using metal-oxide-silicon (MOS) capacitors with thin (14 nm) thermal oxide. Three different metal electrodes were deposited on a thin sputtered Co seed layer: (a) sputtered Al, (b) electroless Co(W,P) and (c) electroless multilayer of Co(W,P)/Cu/Co(W,P). The study includes thermal stress in vacuum in the 300–600°C temperature range, for periods of 30 min to 4 h, followed by electrical characterization. The high-frequency capacitance versus voltage ( C– V) characteristics of the capacitors was near ideal after annealing at 300–500°C for 30 min. After annealing at higher temperatures for longer times the inversion capacitance increased above the ideal high-frequency value while the flat band voltage remained unchanged. The minority carrier lifetime, as obtained from transient capacitance analysis, was in the range of 60 μs for samples annealed at temperatures below 500°C. It dropped for the samples with copper layers to 12 μs after 520°C anneal for 2 h and to 1 μs after 600°C for 4 h while remaining in the range of 50–60 μs for the samples with either electroless barrier or aluminum. AES profiling indicated that the copper profile remained unchanged after annealing at temperatures up to 500°C anneal for 30 min. Above 520°C, the copper profile showed significant diffusion onto the Co(W,P) barrier layer underneath and much less diffusion onto the Co(W,P) capping layer above.