EEPROM Research Articles

A 2-Way Verification Process using One Time Password Key for Home Authentication System By IJISRT

The goal of this research project is to make it possible to implement extra security measures in place of employment and residence.In the suggested system, A 2- way verification technique is applied. First, the data is stored in the Electrically Erasable Programmable Read Only Memory (EEPROM) password for security. If the user enters the correct password, a randomized verification One Time Password or key is sent via paired Bluetooth and user device which is smartphone for 2 - way verification. If the entered key or OTP matches, the system will be opened and the required job may be begun. If either the key or the OTP is entered incorrectly, access is denied and the user can have a few attempts-- three chances under the suggested approach. The main objective is to develop a complete home security system using wireless devices and embedded (micro controller) technology.

White Rabbit Expansion Board: Design, Architecture, and Signal Integrity Simulations

The White Rabbit protocol allows synchronization and communication via an optical link in an integrated, modular, and scalable manner. It provides a solution to those applications that have very demanding requirements in terms of synchronization. Field-programmable gate arrays are used to implement the protocol; additionally, special hardware is needed to provide the necessary clock signals used by the dual-mixer time difference for precise phase measurement. In the present work, an expansion board that allows for White Rabbit functionality is presented. The expansion board contains the oscillators required by the White Rabbit protocol, one running at 125 MHz and another at 124.922 MHZ. The architecture of this board includes two oscillator systems for tests and comparison. One is based on VCOs and another on crystal oscillators running at the desired frequencies. In addition, it incorporates a temperature sensor, from where the medium access control address is extracted, an electrically erasable programmable read-only memory, a pulse-per-second output, and a USB UART to access the White Rabbit IP core at the field-programmable gate array. Finally, to ensure the quality of the layout design and guarantee the level of synchronization desired, the results of the power and signal integrity simulations are also presented.

A CNN-Based E-Nose Using Time Series Features for Food Freshness Classification

In this article, a convolutional neural network (CNN)-based electronic nose system is proposed, which utilizes time series features to classify the freshness of food. The electronic nose is composed of three elements: a highly sensitive miniaturized micro-electromechanical systems (MEMS) metal–oxide (MOX)–semiconductor gas sensor array, a complementary metal–oxide–semiconductor (CMOS) integrated circuit, and a CNN-based classification unit. The gas sensors exhibit exceptional sensitivity, low power consumption, and a small size. The interface circuit for sensor readout is fabricated using a standard 180-nm CMOS process, with an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.5$ </tex-math></inline-formula> mm. The interface chip mainly consists of an analog-to-digital converter (ADC), an electrically erasable programmable read-only memory (EEPROM), an oscillator (OSC), power management, a heater driver, and a digital control circuit. Fixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}{(}{t}{)}$ </tex-math></inline-formula> exposures are taken at specific intervals under gas input and output conditions. Time series features are extracted from a diverse set of sensor signals, which allows the subtle differences in various food odors at different freshness levels to be identified. The incorporation of time series feature extraction extends the data features, resulting in enhanced classification accuracy with a limited number of sensors. An abstract odor map input to the CNN is formed by combining the steady-state and transient information of the gas sensor response. The final freshness classification accuracy of 20 types of foods is 97.3%. The accuracy is improved by 6.5% after the implementation of time series feature extraction, demonstrating the significance of instantaneous fluctuation information for classification accuracy.

Precision Hall Effect magnetometer.

The article presents a Hall effect magnetometer for use in a desktop Electron Paramagnetic Resonance spectrometer with a permanent magnet system and scanning coils. High accuracy and long-term stability at a small size and low cost are achieved through the use of digital signal processing, sequential data filtering in the time and frequency domains, as well as digital correction of raw data based on calibration information. The exciting current of the Hall sensor has the form of an alternating-signsquare wave formed by a high-speed H-bridge powered by a stable direct current. Generation of control signals, time selection of data, and their accumulation are performed using Xilinx Field-Programmable Gate Array Artix-7. MicroBlaze embedded 32-bit processor is used to control the magnetometer and interface with adjacent levels of the control system. Taking into account the individual characteristics of the sensor, including the offset voltage, the nonlinearity of the magnetic sensitivity, and their temperature dependences, is carried out by correcting the data obtained by calculating a polynomial depending on the raw magnitude of the field induction and the temperature of the sensor. The polynomial coefficients are individual for each sensor, are determined once during the calibration process, and are stored in the dedicated Electrically Erasable Programmable Read-Only Memory. The magnetometer has a high resolution of 0.1 µT and an absolute measurement error of not exceeding 6 µT.

EEPROM endurance degradation at different temperatures: State of the art TCAD simulation

Electrically Erasable Programmable Read Only Memory (EEPROM) is a widely used memory device, nowadays implemented in submicron technology nodes. In this paper we show how the well-known trapping power law found in the literature can be retrieved by combining well calibrated state of the art Technology Computer Aided-Design (TCAD) simulations with a compact model for tunnel oxide degradation during EEPROM cycling. We pinpoint how this approach can be used to predictively assess the programming window closure and consequently, considerably reduce the time-consuming cycling test procedure. Finally, we show how this methodology can cover a wide range of temperatures, making it very attractive for high demanding applications such as automotive.

Mesin Penetas Telur Menggunakan Microcontroller ATMega328 Berbasis Arduino

The purpose of this study was to design and implement a duck egg incubator. An egg incubator is a machine that functions to take over the incubation task of a duck mother in incubating fertilized eggs from the result of crossing or mating with a male. The existing incubators work in temperature control, reversing the egg racks, but do not use an egg informing system that has been hatched. In designing this duck egg incubator based on Arduino as a controller. The temperature used must be measured by the resistance of the space or the approximate resistance of the eggs to hatch. The microcontroller used is the ATMega328 integrated on the Arduino Uno, temperature sensor, humidity sensor, humidity control system and other supporting components using Arduino. The test was carried out by comparing the DS18B20 temperature sensor with a Thermometer with an error difference of 0.15. The result of this research is the device can control the temperature not exceeding 39 ° C for hatching eggs. The device has 2 usage buttons, namely a start button (green) to perform hatching day calculations and a reset button (red) to stop hatching day calculations. The day variable that has been running is still stored in the microcontroller EEPROM (Electrically Erasable Programmable Read-Only Memory) so that if there is a disconnection or loss of a voltage power source such as a power failure and so on. The 12VDC fan on the device turns on every 30 minutes and goes out for the next 30 minutes

A Digital Improvement-Trimming a Digital Temperature Sensor with EEPROM Reprogrammable Fuses.

An EEPROM (electrically erasable programmable read-only memory) reprogrammable fuse for trimming a digital temperature sensor is designed in a 0.18-µm CMOS EEPROM. The fuse uses EEPROM memory cells, which allow multiple programming cycles by modifying the stored data on the digital trim codes applied to the thermal sensor. By reprogramming the fuse, the temperature sensor can be adjusted with an increased trim variation in order to achieve higher accuracy. Experimental results for the trimmed digital sensor showed a +1.5/−1.0 ℃ inaccuracy in the temperature range of −20 to 125 ℃ for 25 trimmed DTS samples at 1.8 V by one-point calibration. Furthermore, an average mean of 0.40 ℃ and a standard deviation of 0.70 ℃ temperature error were obtained in the same temperature range for power supply voltages from 1.7 to 1.9 V. Thus, the digital sensor exhibits similar performances for the entire power supply range of 1.7 to 3.6 V.

Design of Phototherapy Radiometer with a Measurement Stability Improvement

The amount of radiation given from the phototherapy lamp (Blue Light) who not right for neonates with hyperbilirubin is feared to cause the bilirubin levels in not decrease accordance with the calculated dose. The purpose of this study is to make a Blue Light calibration device with a stable measurement. The contribution of this research is by determine a sensor who able to measure the irradiation value more accurately between TCS3200 and AS7262 sensor. TCS3200 sensor measures the wavelengths of 470nm, 524nm and 640nm and AS7262 sensor can measure wavelengths of 430-670nm. The results of both sensors are stored in the Electrically Erasable Programmable Read-Only Memory, with the amount of data and the length of measurement can be adjusted according to user needs. Measurement the irradiation value of two sensors is done simultaneously using 3 Watt Light Emitting Diode lamp as a Blue Light simulation where the lamp is placed directly above the sensor and distance of the lamp to the sensor is 10cm, 20cm, 30cm, and 40cm. The average uncertainty value with TCS3200 sensor is 14.65 and the average uncertainty value with AS7262 sensor is 2.17. Type A uncertainty value is based on results of repeated measurements that show how close the measurement results are to the actual value (stable measurement results). The results showed that the average uncertainty value on AS7262 sensor is relatively small, so its mean the measurement results of AS7262 sensor are stable. The author suggests using sensors who capable of reading the value of light radiation without conversion. The results of this study can be implemented to measure the intensity of the lamp and be used as a reference to determining the time of lamp replacement.

Integrated Prognostics Observer for Condition Monitoring of an Automated Manual Transmission Dry Clutch System

The closed loop feedback control system of an Automated Manual Transmission (AMT) electro-pneumatic clutch actuator is used for intelligent real time condition monitoring, enhanced diagnostics and prognostic health management of the dry clutch system, by integrating with the existing gearbox prognostics observer. The real-time sensor data of the clutch actuator piston position is analyzed for monitoring the condition of the clutch system. Original parameters of the new clutch are stored in the Electrically Erasable Programmable Read-only Memory (EEPROM) of the AMT controller and the real-time data is used by the observer for assessing the degradation/wear of the frictional clutch parts. Also, clutch slip during torque transmission is monitored, using the engine speed and the gearbox input shaft speed from Controller Area Network (CAN). Condition monitoring of clutch system provides enhanced prognostic functionality for AMT system which ensures consistent clutch performance, gear shift quality and timely warning for recalibration, repair and/or replacement of the critical wear and tear parts. Also, systematic analysis of the monitored data provides an accurate diagnosis of a developing fault. Thus, with the advanced control systems in place for AMT, a closed loop feedback based condition monitoring system is modelled for improved diagnostics and prognostics of AMT clutch system.

Improving the Performance of RLizard on Memory-Constraint IoT Devices with 8-Bit ATmega MCU

We propose an improved RLizard implementation method that enables the RLizard key encapsulation mechanism (KEM) to run in a resource-constrained Internet of Things (IoT) environment with an 8-bit micro controller unit (MCU) and 8–16 KB of SRAM. Existing research has shown that the proposed method can function in a relatively high-end IoT environment, but there is a limitation when applying the existing implementation to our environment because of the insufficient SRAM space. We improve the implementation of the RLizard KEM by utilizing electrically erasable, programmable, read-only memory (EEPROM) and flash memory, which is possessed by all 8-bit ATmega MCUs. In addition, in order to prevent a decrease in execution time related to their use, we improve the multiplication process between polynomials utilizing the special property of the second multiplicand in each algorithm of the RLizard KEM. Thus, we reduce the required MCU clock cycle consumption. The results show that, compared to the existing code submitted to the National Institute of Standard and Technology (NIST) PQC standardization competition, the required MCU clock cycle is reduced by an average of 52%, and the memory used is reduced by approximately 77%. In this way, we verified that the RLizard KEM works well in our low-end IoT environments.

Security Enhancement for Building Access, Using One Time Password (OTP) Technology

Ubiquitous as mobile technologies are, and the various advancements the technologies have experienced, makes the field pertinent for integration into security systems of buildings. As a security enhancement technique for building access, this project was proposed as a way of paving a way for integration of one time password (OTP) technology using microcontroller to security systems. In addition, the proposed project will be a supplement to the challenges of other security authentication methods centered on Bluetooth, radio frequency identification (RFID), biometrics and voice recognition techniques. In other to reduce complexity in design, a microcontroller was introduced to hub the coordination of the system. The two way verification system which can be coupled with aforementioned security systems, boast of its ability to store numeric identity of each authorized user to a building in the electrical erasable programmable read only memory (EEPROM) of the microcontroller. The system prompt a user wanting to gain access to the building through the door to input designated numeric identity (password) stored in data base. Once the inputted designated numeric identity entered matches an identity in the data base, then for the second verification process, a randomly generated OTP which has a programmed validity of three minutes is sent to the user phone via a GSM (global system for mobile communication) module. If either the password or OTP entered doesn’t match, then access is denied and the user will only be relegated to two limited successful chances with time duration as programmed for retrial before the system reset for the next user. Once there is failure at any stage of verification outside prescribed attempted limit, an alarm is sounded with implication that a burglar is attempting entry. Electric power to the project was driven from an ac mains which was then rectified to power all the dc dependent components used. The low construction cost, user friendliness, flexibility, insured security when compared to other security systems, makes the inovation unique.

Restoring Stephan Von Huene's Tap Dancer: Finding Logic within Integrated Circuits

ABSTRACT Stephan von Huene is recognized for his acoustical sculptures that combine movement and sound with the flip of a switch. This paper will focus on his Tap Dancer (1967) composed of cropped legs in pants and shoes on a wooden base that perform a 30-second tap dance at regular intervals. The movement and sound are controlled by integrated circuit boards wired to valves, a vacuum and recycled musical components. The condition of the wiring and circuitry is critical to allow the performance, which is intended to be random by way of an erasable programmable read-only memory (EPROM) and timing circuit. Von Huene's sculptures have conservation issues when exhibited and plugged in for action. Challenges arose during the exhibition of Tap Dancer at the J. Paul Getty Museum in Los Angeles leading to conservation interventions including the adaptation of EPROM data to a solid-state controller. After exhibition at the Getty, the temporary solutions were replaced with a full restoration of the original circuit boards repairing wiring or damaged chips as needed. The history of Tap Dancer has shown that with the desire to exhibit von Huene's works as intended, the endurance of their structures is inevitably at risk.

A system verilog approach for verification of memory controller

&lt;span&gt;Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.&lt;/span&gt;

A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM.

A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID–EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.

Innovative and rapid design for I2C (inter-integrated circuit) interface communication of FPGA chips

A new design flow is proposed to greatly improve the efficiency and accuracy of the HDL program design. This paper successfully completes the FPGA (Field-Programmable Gate Array) chip’s external communication I2C interface design of new design flow not traditionally one. FPGA chip is often used in mobile phones, military, aerospace or other industries. Even INTEL and Microsoft and other large companies have begun to acquire FPGA-related companies, showing its importance. But the FPGA language is written in the Hardware Description Language (HDL) which is a mechanical engineering staff obstacles. Therefore, this article makes use of the MATLAB / SIMULINK tool, which is familiar with the engineering staff, to complete the FPGA chip’s I2C interface design. The advantage is that the functional simulation and HDL program can be completed at the same time, do not have to perform the function after the simulation before designing HDL program. The traditional design wastes many times to revise back and forth between function simulation and HDL program design. Finally an experimental illustration is proposed to verify the proposed design of the I2C communication interface for an HDL program on the read and write experiments of Electrically-Erasable Programmable Read-Only Memory (EEPROM).

An efficient Verilog-A memristor model implementation: simulation and application

Complementary metal–oxide–semiconductor (CMOS) technology is reaching its limits due to the continuous shrinking process, which has an impact on various aspects including device size, performance, and power consumption. The memristor is one of the promising devices under investigation for use with deep-nanometer CMOS, having applicability in several fields due to its nonlinear behavior, nonvolatility, low power consumption, high density, and CMOS compatibility. Several models for memristors have been developed to date, but there is a requirement for compact models that are both flexible and sufficiently accurate. A general memristor model generated in Verilog-A is discussed herein to confirm its behavior in the one-transistor one-resistor (1T1R) oxide-based random-access memory (OxRAM) configuration, and validated at circuit level. The results of the model correlate well with experimental characterization data for the HfO2-based OxRAM memristor device, describing the characteristics of both its bipolar and unipolar memristor behaviors. The 1T1R structure is analyzed using the Spectre circuit simulator. Two cases are considered, using the cell as either programmable read-only memory (PROM) or electrically erasable programmable read-only memory (EEPROM). The simulation results confirm the desired nonlinear memristor characteristic, and the applicability of the model to fit and simulate different switching behaviors. The results are verified against both electrical and experimental characterization data, suggesting that the Verilog-A model is suitable for low-power and high-density logic circuit applications at the industrial level.

Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

Conceptual implementation of a data logger with a graphical user interface data extraction program

&lt;span lang="EN-MY"&gt;A Graphical User Interface (GUI) design was developed to extract data from a data logger. The low-cost data logger was developed using a common pic18f4550 microcontroller. Simple data recording feature is implemented by using the &lt;/span&gt;&lt;span&gt;Electrically Erasable Programmable Read-Only Memory (&lt;/span&gt;&lt;span lang="EN-MY"&gt;EEPROM) module from the microcontroller unit. The GUI software employed VB.net 2013 and has been tested to work in window 10 environment. Simulation work was performed with temperature and humidity sensors using Proteus VSM software. Upon simulation, the GUI shows its capability of extracting measured data from the data logger and converting the data to a Comma-Separated Values, (CSV) format for further analysis.&lt;/span&gt;

The Smart Card – An Authentic &amp;amp; Secure Elearning ICT Toolkit

In this era of information technology, browsing information and the concept of information on the human mind and attitude has bombarded from all sides, which won’t allow any human being to escape from the invisible pitfall of information. In order to streamline this aggressive mode of information sciences at this defining moment, the gravity of the situation must be analyzed accurately. On one side it had shaken the ideological bases of our nation while on the other it provides and fulfills the realization of a fundamental right i.e “education for all”. With the institutionalization of this golden opportunity, the literacy rate can easily be made 100% in a short span of time. Despite the insufficient budget, technology can easily materialize the motto of education for all. Failing which the multinational corporations and agencies will fill the vacuum in an unwanted way. These organizations with their terrible tentacles and enormous financial assets will alter our national identity. They will drain our brains to their own countries and will train them according to their needs. The aim of this study is to spread the use of a simple tool called “smart card” used for personal communication like distance learning and eLearning. A smart card is a small computer with its own Operating System, Random Accesses Memory (RAM), Electrically Erasable Programmable Read-Only Memory (EEPROM) and a small memory for storing high cryptographic functions and is capable of storing, managing, controlling and conveying information in a significant manner.

Frequency Offset-Based Ring Oscillator Physical Unclonable Function

Weak Physical Unclonable Function (PUF) is a promising lightweight hardware security primitive that is used for secret key generation without the requirement of secure nonvolatile electrically erasable programmable read-only memory (EEPROM) or battery backed static random-access memory (SRAM) for resource-limited applications such as Internet of Thing (IoT) and embedded systems. The Ring Oscillator (RO) PUF is one of the most popular weak PUFs that can generate the volatile key by comparing the frequency difference between any two ROs. However, it is difficult for the RO PUF to maintain an absolutely stable response with operating environment varies. In order to eliminate the impact of environment factors, previous RO PUFs incur significant hardware overheads to improve the reliability. This paper proposes a frequency offset-based RO PUF structure which exhibits high reliability and low hardware overhead. The key idea is to make the frequency difference larger than a given threshold by offsetting the frequencies of RO pairs to improve reliability. Prototype implementation on Xilinx 65 nm Field-programmable Gate Arrays (FPGAs) shows the low overhead of the new structure and 100 percent reliability with temperature range of 45 $^\circ \mathrm{C}$ $\sim$ 95 $^\circ \mathrm{C}$ .