Electrically Erasable Programmable Read-only Memory Cell Research Articles

Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory

A 200-KB embedded electrically erasable programmable read -only memory (EEPROM), which operates with a single 1.5-V power supply voltage based on an HHGRACE (Shanghai Huahong Grace Semiconductor Manufacturing Corporation) 90-nm EEPROM process, is developed. In this brief, several key design techniques are presented. An improved bit cell with a larger current sensing window is adopted in the split-source EEPROM array. To get high-speed read operation, a high-performance sense amplifier and a dynamic sensing window tracking reference voltage generating circuit have been proposed. The die size of the proposed EEPROM IP is 1.271 mm2, and the EEPROM cell size is 0.32 $\mu\text{m}^{2}$ . Access time of 30 ns is achieved at 1.5 V and 25 °C.

Performance improvement of the EEPROM cells with the standard logic process featuring a metal finger coupling capacitor

In this paper, a novel single-poly electrically erasable programmable read-only memory (EEPROM) using a metal finger coupling capacitor is proposed and fabricated with a pure logic CMOS process. The metal interconnect layer is applied to form the finger-type capacitor which can be used as the coupling capacitor in the EEPROM cell. Using the metal finger capacitor, the proposed cell exhibits the advantages of a metallic control gate and features a higher coupling ratio to achieve smaller cell area and lower program/erase voltage. The program/erase characteristics, endurance and retention performances are presented. In addition, the EEPROM cell with a stacked metal finger structure can further improve the coupling ratio. Thus, lower operation voltage can be obtained without increasing the cell area.

TCAD-based demonstration of improved spacer select gate EEPROM cell architecture

An SSG EEPROM (Spacer Select Gate Electrically Erasable Programmable Read Only Memory) cell is proposed for improvement in program and erase operations and compared with a conventional one. Electrical characteristics of the conventional SSG EEPROM cell in program and erase operations are simulated, analyzed, using TCAD software tools, and verified against measurements. The improved SSG EEPROM cell reaches a target threshold voltage 3.9 V at 0.26 ms after the program operation starts, whereas the conventional cell at 1.7 ms. The Fowler–Nordheim tunneling current and floating gate charge of the improved EEPROM cell during the program operation are 5 times and 46% larger than those of the conventional cell, respectively. Scaling down the SSG EEPROM cells improves both the program and erase speeds. As the floating gate length of the conventional SSG EEPROM cell is reduced from 0.21 to 0.1 μm, the 0.1-μm EEPROM cell reaches the target program threshold voltage 25 times faster than the 0.21-μm cell.

Enhanced Planar Poly-Si TFT EEPROM Cell for System on Panel Applications

In this work an enhanced electrically erasable programmable read-only memory (EEPROM) device comprised of twin low-temperature poly-Si thin-film transistors (TFTs) was fabricated for potential application to system-on-panel technology. Also, two kinds of memory devices with different overlap areas were developed to investigate the gate-coupling effect. The memory window of 4.8 and 4 V can be obtained at a programming voltage of 18 V, separately, for the fully overlapped EEPROM and the one with a 1 μm length overlap between the gate and source/drain. The excellent memory characteristics of the fully overlapped TFT EEPROM cell are attributed to the enhanced gate-coupling ratio by maximizing the overlap coverage between the gate electrode and the source/drain regions.

Effect of H 2O evolving from TEOS based SiO 2 film on the EEPROM cell characteristic

In this paper, we investigate the effect of water (H 2O) molecules evolving from silicon dioxide (SiO 2) film deposited by low pressure chemical vapor deposition (LPCVD) at 670 °C on the transistor characteristic of an electrically erasable programmable read only memory (EEPROM) cell. Fourier Transform Infra red (FT-IR) analysis reveals that H 2O is captured during film deposition and diffused to silicon surface during high thermal processing. The diffused H 2O molecules lower threshold voltage ( V t) of cell transistor and, thus, leakage current of the cell transistor is increased. In erased cell, V t lowering is 0.25 V in which it increases leakage current of cell transistor from 1 to 100 pA. This results in the lowering of high voltage margin of a 512 Kb EEPROM from 2.8 to 2.6 V at 85 °C.

Towards a model linking tunnel oxide degradation to programming window closure in EEPROM cells

One of the main reliability problem in electrically erasable programmable read only memory (EEPROM) devices is the progressive closure of the programming window as the number of applied write/erase cycles is increased. This closure is qualitatively attributed to the build-up of fixed negative charge in the tunnel oxide during Fowler–Nordheim (FN) electron injection. Electron trapping induces FN current voltage shifts and consequently variations of the charge accumulated into the floating gate during one programming operation. In this work, we present an analytical quantitative model linking these shifts representative of oxide charging, to EEPROM cells threshold voltages in programmed states. This model is based on a simple electrical equivalent circuit and predicts a linear relationship between threshold and FN injection voltages shifts. The proportional constant is only dependent on the control gate–floating gate capacitive coupling ratio. Using a specific EEPROM-like test structure, the proposed model has been experimentally validated.

A new physical-based compact model of floating-gate EEPROM cells

A model for static and transient simulations of an electrically erasable programmable read-only memory (EEPROM) cell has been developed. This physical compact model is based on charge sheet approach which is able to describe the complete electrical properties of the cell. In this model the charge neutrality, including the charge trapped on the floating gate, is applied to determine the surface potential. From the surface potential, related to the terminal voltages, the drain current and the different charges present in the cell structure can be calculated. This model has been successfully implemented in common circuit simulators (Eldo and Saber) and used for the study of the write/erase operations in an EEPROM cell.

Improvement of EEPROM cell reliability by optimization of signal programming

This paper presents an optimization study of electrically erasable programmable read-only memory (EEPROM) cell programming to increase the long-term reliability of the device. Based on a charge-sheet model of the memory cell, we suggest that our result show that it is possible to decrease the electric field across the tunnel oxide of approximately 0.8 MV/cm, when using a particular programming waveform with a double rise ramp. We get the same simulated injected charge in write mode (+15 fC) and in erase mode (−12 fC) with the optimized programming signal rather than with the standard one. Threshold voltage measurements confirm the simulation results. Moreover, the endurance test shows that this new programming signal improves the endurance of the memory cell without any change in the device technology, memory cell lifetime becomes four times longer.

Dynamic stressing of thin tunnel oxides: a way to emulate a single EEPROM cell programming function

An experimental set-up was implemented by which metal-oxide-semiconductor (MOS) capacitors are subjected to bipolar high voltage (up to 20 V) pulses similar to those used in programming electrically erasable programmable read-only memory (EEPROM) devices. Thin (9 nm) tunnel SiO 2 oxides MOS capacitors were used. During stress, by means of capacitive coupling, the capacitors gate node was kept floating so its potential was equivalent to that of the isolated floating gate of a memory cell. The written and erased operations of memory cells which are based on Fowler–Nordheim (FN) tunneling injection mechanisms, were then reproduced on simple MOS capacitors. Via a high input impedance electronic circuit, the floating gate potential was monitoring. A model based on a simple equivalent electrical circuit was used to simulate the transient regime of the FN current and the resulting floating gate charge and potential during dynamic stressing. It was shown that the floating gate accumulated charge is proportional to the maximum control gate voltage but is independent of the control gate pulse rise time.

Advanced electrical-level modeling of EEPROM cells

Conventional modeling of floating-gate electrically erasable programmable read-only memory (EEPROM) cells is shown to be inadequate to correctly evaluate the tunnel current flowing through the MOS injector during programming, essentially because of relevant quantum phenomena taking place at the cathode semiconductor-oxide interface. An electrical-level model incorporating numerical analysis of such effects is developed and discussed. The model is validated by comparing results of the simulations with experimental data obtained with EEPROM cells. The model of the MOS injector has been implemented in the circuit simulator SPICE.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 0.5- mu m EEPROM cell using poly-Si TFT technology

A 0.5- mu m EEPROM (electrically erasable programmable read only memory) cell using poly-Si thin-film transistor (TFT) technology is reported. 10- mu s programming time and a good endurance over 10/sup 4/ program/erase cycles were obtained. These device characteristics are promising for low-cost and high-density EEPROMs.

The impact of three-dimensional effects on EEPROM cell performance

Device simulation is used to investigate three-dimensional effects in small electrically erasable programmable read-only memory (EEPROM) cells. Threshold voltage, tunnel currents, write speed, and the effects of misregistration are characterized for a structurally parameterized generic FLOTOX EEPROM cell. The results indicate considerable sensitivity to three-dimensional effects. Design insights for small EEPROM cells are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A million-cycle CMOS 256 K EEPROM

A single 5-V supply 256 K EEPROM (electrically erasable programmable read-only memory) was designed, manufactured, and tested. A recently developed double-poly n-well CMOS process with 1.25-/spl mu/m minimum feature size was successfully used to manufacture this part. Using this technology, a 54-/spl mu/m/SUP 2/ EEPROM cell has been realized. A novel autoredundant Q-cell concept used in the memory core combined with the very-high-endurance oxynitride dielectric provides the breakthrough needed to increase the endurance of the 256 K EEPROM up to one million write cycles. Descriptions of the internal timer, all relevant programming signals, the byte/page switch, the bit and byte latches, the sense amplifier, and the CMOS EE fuses give insight into the complexity of the peripheral circuits. The measured device performance and the chip architecture description are presented.