Performance improvement of the EEPROM cells with the standard logic process featuring a metal finger coupling capacitor

Abstract

In this paper, a novel single-poly electrically erasable programmable read-only memory (EEPROM) using a metal finger coupling capacitor is proposed and fabricated with a pure logic CMOS process. The metal interconnect layer is applied to form the finger-type capacitor which can be used as the coupling capacitor in the EEPROM cell. Using the metal finger capacitor, the proposed cell exhibits the advantages of a metallic control gate and features a higher coupling ratio to achieve smaller cell area and lower program/erase voltage. The program/erase characteristics, endurance and retention performances are presented. In addition, the EEPROM cell with a stacked metal finger structure can further improve the coupling ratio. Thus, lower operation voltage can be obtained without increasing the cell area.