Abstract
A triple modular redundant (TMR) electrically erasable programmable read only memory (EEPROM) cell design used for on-chip error correction is described. It can be used in applications where high reliability and high endurance are required. A mathematical reliability model used to assess the effectiveness of this fault-tolerant structure is also presented. Since the TMR EEPROM cell is available in a standard-cell semicustom integrated circuit (IC) family, the model can be used to assess fault tolerance for any semicustom ICs which use the fault-tolerant EEPROM circuitry. The fault-tolerant scheme is shown to provide endurance and reliability beyond that for EEPROM cells which do not have on-chip error correction. >
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