A million-cycle CMOS 256 K EEPROM

Abstract

A single 5-V supply 256 K EEPROM (electrically erasable programmable read-only memory) was designed, manufactured, and tested. A recently developed double-poly n-well CMOS process with 1.25-/spl mu/m minimum feature size was successfully used to manufacture this part. Using this technology, a 54-/spl mu/m/SUP 2/ EEPROM cell has been realized. A novel autoredundant Q-cell concept used in the memory core combined with the very-high-endurance oxynitride dielectric provides the breakthrough needed to increase the endurance of the 256 K EEPROM up to one million write cycles. Descriptions of the internal timer, all relevant programming signals, the byte/page switch, the bit and byte latches, the sense amplifier, and the CMOS EE fuses give insight into the complexity of the peripheral circuits. The measured device performance and the chip architecture description are presented.