Electrical Oxide Thickness Research Articles

Influence of I/O oxide process on the NBTI performance of 28 nm HfO2-based HKMG p-MOSFETs

The NBTI (negative bias temperature instability) performance of 28nm HfO2-based HKMG (high-κ metal gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (in-situ steam generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (post deposition anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (decoupled plasma nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (electrical oxide thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements.

Electrically Scaled Hafnium Oxide Based Ge Devices

As device feature sizes have continued to scale, new device engineering and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations in reducing short channel effects and improved performance are through the introduction of FinFETs, nanowires, and high mobility channel materials. High mobility channel materials, such as Ge and III-V (InGaAs, GaAs), are attracting increasing interest due to the possibility of realizing increased performance even without scaling the gate length of the device (1-3). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing compatibility. In this paper we report progress in high-k phase engineering through HfO2:ZrO2 doping combined with intermittent annealing and post deposition microwave plasma oxidation in order to achieve sub nm EOT with reasonable leakage. In this regard, 300mm epi Ge/Al2O3/ZrO2/TiN MOSCAP devices were fabricated using epitaxially grown Ge. We have utilized a TEL CertasTM Chemical Oxide Removal (COR) process (4), which uses anhydrous HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. The high-k stack Al2O3/HfxZr1-xO2 were deposited by atomic layer deposition on a TEL Triase +TM tool. The ALD HfxZr1-xO2 films were deposited using a cyclical deposition and annealing scheme (termed DADA) (5-6). Prior to the ALD HfxZr1-xO2 a thin ALD Al2O3 was deposited. An additional post microwave plasma oxidation was also carried out in situ. A post plasma Al2O3/ZrO2control sample with no DADA process was also fabricated. Figure 1 shows electrical leakage Jg vs equivalent oxide thickness (EOT). The electrical analysis show a scaled EOT of ~0.6nm with the combination of DADA and post plasma oxidation compared to the control sample with only post plasma oxidation processed, see Fig.1. In addition, DADA processed samples without additional post plasma oxidation (6) resulted in very high leakage. The impact of post plasma oxidation and DADA on the electrical and physical characteristics of the Hf based dielectrics will be discussed in detail.

Diffusion and Gate Replacement: A New Gate-First High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula>/Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow.

A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies

In this work the threshold voltage (Vt), the current gain factor (β), and the drain current (ID) mismatch trends for 20nm Gate-Last bulk CMOS technology integrating High-k/metal gate are investigated. The reported results indicate that the high k/metal Gate-Last technology exhibits a reduced metal gate granularity contribution to the Vt mismatch and good performance in terms of the β mismatch. This study further demonstrates that the ID variability mainly depends on the mismatch trends of Vt and β, and on the contributions of the transconductance divided by the drain current (Gm/ID) and the source drain series resistance (Rsd) terms. The 20nm Gate-Last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28nm Gate-First counterpart. The evolution of the Vt and β mismatch parameters, iAΔVt and iAΔβ/β, is further analyzed as a function of the electrical oxide thickness EOT (Tox) along the technology nodes from 90nm to 20nm. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot of iAΔVt as a function of EOT is observed starting at the 28nm Gate-First technology, with the offset approaching zero for the 20nm Gate-Last technology node. This observation point out a considerable decrease of the gate material contribution to mismatch performances.

Pioneering Application of Corona Charge-Kelvin Probe Metrology to Noncontact Characterization of In0.53 Ga0.47 As/Al2O3/HfO2 Stack

ABSTRACTWe report the first successful application of corona charging noncontact C-V and I-V metrology to interface and dielectric characterization of high-k/III-V structures. The metrology, which has been commonly used in Si IC manufacturing, uses incremental corona charge dosing, ΔQC, on the dielectric surface, and the measurement of surface voltage response, ΔVS, using a Kelvin-probe. Its application to In0.53Ga0.47As with a high-k stack required modifications related to the effects of dielectric trap induced voltage transients. The developed Corona Charge-Kelvin Probe Metrology adopted strictly differential measurements using ΔQC and ΔV, and corresponding differential capacitance rather than measurements based on total global charge, Q, and voltage, V, values.Electrical characterization data including interface trap density, electrical oxide thickness, and dielectric leakage are presented for a sample containing an In0.53 Ga0.47 As channel overlaid with a bilayer (2nm Al2O3/5nm HfO2) dielectric stack that is considered to be very promising for application in performance NFETs with high-mobility channels.

Impact of quantum effects on the short channel effects of III–V nMOSFETs in weak and strong inversion regimes

This paper investigates the impact of quantum effects on the increase of short channel effects in III–V MOSFETs. First of all, contrary to the results obtained by other groups [1,2], quantum confinement has been found to play no role on the short channel effects occurring in the subthreshold regime. In this regime, the main origin of the increase of SCEs is simply due to the higher dielectric constant of III–V semiconductors. However, in strong inversion regime, the increase of the electrical equivalent oxide thickness due to quantum confinement is shown to have a detrimental impact on the drain induced barrier lowering. These results further confirm that III–V technologies will require innovative devices like ultra-thin films or multi-gate structures to ensure a better control short channel effects.

Comprehensive Understanding on the Role of Tunnel Oxide Top Nitridation for the Reliability of Nanoscale Flash Memory

We report the role of tunnel oxide (TO) top nitridation (TN) in the reliability of nanoscale Flash memory and provide comprehensive understanding for the mechanism. TN was expected to potentially improve the TO quality by protecting against damages from edge encroachment and other processes. However, instead of net improvement, we found a tradeoff between endurance (charge trap) and retention (charge detrap and leakage) in the reliability of the cell array. We find that more charges are trapped in the TO with increasing nitrogen concentration, although detrapping can be decreased in a limited concentration. This suggests that the defect in the TN layer (SiON) includes a deep energy trap, thus resulting in a more strongly bound charge. Increasing nitrogen concentration also degrades charge retention from TO leakage but can be better for the same electrical oxide thickness. Evaluating a band diagram suggests that the possible improvement arises from the greater physical oxide thickness, although the barrier height for electron transmission is lower. This suggests that TO leakage is dominated by an inelastic trap-assisted tunneling mode using multiple direct tunneling through deep oxide traps. The results are indicative of the intrinsic impact of TN, regardless of bulk nitrogen or hydrogen incorporation.

Barrier-Engineered Arsenide–Antimonide Heterojunction Tunnel FETs With Enhanced Drive Current

In this letter, we experimentally demonstrate enhancement in drive current <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> and reduction in drain-induced barrier thinning (DIBT) in arsenide-antimonide staggered-gap heterojunction (hetj) tunnel field-effect transistors (TFETs) by engineering the effective tunneling barrier height Eb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> from 0.58 to 0.25 eV. Moderate-stagger GaAs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.65</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.35</sub> As (Eb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> = 0.31 eV) and high-stagger GaAs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.35</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.65</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As (Eb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> = 0.25 eV) hetj TFETs are fabricated, and their electrical results are compared with the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As homojunction (homj) TFET (Eb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> = 0.58 eV). Due to the 57% reduction in Eb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> , the GaAs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.35</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.65</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As hetj TFET achieves 253% enhancement in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> over the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As homj TFET at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> = 1.5 V. With electrical oxide thickness (Toxe) scaling from 2.3 to 2 nm, the enhancement further increases to 350 %, resulting in a record high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of 135 μA/μm and 65% reduction in DIBT at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V.

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> ) continuously scales down as technology advances. Furthermore, the A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INV</sub> ) , threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> variability in the present HKMG technology.

Afterglow Chemical Processing for Oxide Growth on Silicon Carbide

AbstractThe unique capabilities and characteristics provided by afterglow or remote plasma chemical oxide growth processing of silicon carbide are reviewed. Such processing provides for thermal growth of oxide films at temperatures far below those employed by conventional atmospheric processing methods. Overshadowing this growth capability is the ability to create chemistries, sequential procedures, and specific process environments to address material and defect issues in a manner not possible under conventional atmospheric conditions. The details and outcomes of multi-step afterglow oxidation processing of SiC will be discussed. An example sequence might include; 1) surface conditioning, 2) film growth at 850C and 1 Torr total pressure, and 3) reduced pressure unexcited media post-growth treatments. Surface conditioning impacts the thickness uniformity of the final oxide film and the oxidation rate. The film growth interval produces a nominal 500Å of oxide film in 90 minutes at 850C, a temperature that would not produce any significant oxide film at atmospheric pressure. And the post-growth processing improves the performance of the dielectric film. Using in-line corona-Kelvin metrology the electrical characteristics stemming from these processes have been determined. Electrical effective oxide thickness results were used to assess thickness uniformity and to estimate process rate constants for comparison to other process methods. Fowler-Nordheim, F-N, characteristics determined with the same metrology demonstrate that afterglow, AG, oxides require higher field levels to produce the same F-N current as thermal oxides and that AG films are less susceptible to stress fluence. Process extensions from these and other results are discussed and related to chemical, physical, and electrical film outcomes and potential pathways to improve control over dielectric SiC structures.

Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials

AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.

Novel Laser Annealing Process for Advanced Complementary Metal Oxide Semiconductor Devices with Suppressed Polycrystalline Silicon Gate Depletion and Ultra shallow Junctions

One of the major challenges in advanced complementary metal oxide semiconductor (CMOS) technology is to achieve an adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. We investigated gate pre annealing by laser thermal process (LTP) in conjunction with laser spike annealing (LSA) source/drain (S/D) activation to effectively suppress poly-Si gate depletion while forming highly activated ultra shallow junctions for S/D. We found that carrier concentration at the poly-Si gate/gate oxide interface increases and, accordingly, electrical inversion oxide thickness (Tinv) decreases whereas dopant penetration into the Si substrate is suppressed to a level far below that in conventional rapid thermal annealing (RTA). We realized improved device performance characteristics such as a high drive current, a small threshold voltage (Vth) shift, and a reduced off current (Ioff).

Effects of High-$\kappa$ (HfO$_2$) Gate Dielectrics in Double-Gate and Cylindrical-Nanowire FETs Scaled to the Ultimate Technology Nodes

In this work we investigate the performance of double-gate and cylindrical nanowire FETs with high-kappa gate dielectrics at their extreme miniaturization limits. The model fully accounts for quantum electrostatics; current transport is simulated by an improved quantum drift-diffusion approach supported by a new thickness-dependent mobility model which nicely fits the available measurements for both SiO2 and HfO2 gate dielectrics. The on-current is simulated using both the quantum drift-diffusion model and a full-quantum transport approach based on the quantum transmitting boundary method, which assumes a purely ballistic transport. The performance comparison between SiO2 and HfO2 insulated-gate FETs with the same electrical oxide thickness demonstrates that the latter provides a slight degradation of the short-channel effect compared with the former but, at the same time, gives an improved on-current due to lateral capacitive-coupling effects, despite the inherent degradation of the low-field mobility

C-AFM-based thickness determination of thin and ultra-thin SiO2 films by use of different conductive-coated probe tips

The influence of the probe tip type on the electrical oxide thickness result was researched for four differently coated conductive tip types using SiO2 (oxide) films with optical thickness of 1.7–8.3 nm. For this purpose, conductive atomic force microscopy (C-AFM) was used to measure more than 7200 current–voltage (IV) curves. The electrical oxide thickness was determined on a statistical basis from the IV-curves using a recently published tunnelling model for C-AFM application. The model includes parameters associated with the probe tip types used. The evolution of the tip parameters is described in detail. For the theoretical tip parameters, measured and calculated IV-curves showed excellent agreement and the electrical oxide thickness versus the optical oxide thickness showed congruent behaviour, independent of the tip type. However, differences in the electrical oxide thickness were observed for the different tip types. The theoretical parameters were modified experimentally in order to reduce these differences. Theoretical and experimental tip parameters were compared and their effect on the differences in the electrical oxide thickness is discussed for the different tip types. Overall, it is shown that the proposed model provides a comprehensive framework for determining the electrical oxide thickness using C-AFM, for a wide range of oxide thicknesses and for differently coated conductive tips.

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.

Capacitance–Voltage Measurement Method for Ultrathin Gate Dielectrics Using LC Resonance Circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.

Characterization of field-effect transistors with La2Hf2O7 and HfO2 gate dielectric layers deposited by molecular-beam epitaxy

The electrical properties of La2Hf2O7 (LHO) and HfO2 (HO) high-k dielectric layers deposited by molecular-beam epitaxy are reported. Capacitors and transistors with LHO and HO gate dielectric layers and TaN metal gate electrodes deposited using physical vapor deposition were fabricated. The (SiO2) equivalent oxide thickness (EOT), the electrical oxide thickness in inversion toxinv, and the gate leakage current density (Jg) were determined on large area metal-oxide-semiconductor capacitors and metal-oxide-semiconductor field-effect transistors. HO layers with a physical thickness tph=30Å showed an EOT (toxinv) of 15.1Å (19.3Å) with Jg=8.1×10−6A∕cm2 at Vg=Vfb−1V. LHO layers deposited on SiON showed a minimum EOT (toxinv) of 18.7Å (25Å) with Jg=4×10−8A∕cm2 at Vg=Vfb−1V. The (effective) electron mobility at high E field for LHO layers was observed for a 40-Å-thick LHO layer deposited on Si with μeff=147cm2∕Vs at E=1MV∕cm. For a 30-Å-thick HO layer at identical field, μeff=170cm2∕Vs was found. LHO layers deposited on SiON interface exhibited 5%–10% higher electron mobility at high E field than identical layers deposited on Si. Further, both low E field and high E field mobilities decreased for thicker high-k layers, indicating remote charge scattering from both the interface and the bulk of the high-k dielectric. It was observed that LHO layers showed strongly reduced electron trapping in preexisting bulk defects as compared to HO layers. At E=1MV∕cm (corresponding to Vg=VT+0.6V), the trapped charges per area Ntr were Ntr&amp;lt;5×1010∕cm2 for the LHO layers and Ntr&amp;gt;5×1011∕cm2 for the HO layers. These results show that low-leakage Hf-based gate dielectric layers with low defect density can be obtained by alloying with La.

Effects of Low-temperature NH3 Treatment on the Characteristics of HfO2 ∕ SiO2 Gate Stack

The effects of postdeposition low-temperature treatment (LTN treatment) on the characteristics of the gate stack with the TiN gate electrode were studied in this work. After the films were deposited using an AIXTRON Tricent atomic vapor deposition system, the LTN treatment was performed prior to the postdeposition annealing (PDA) step to prevent the growth of an additional interfacial layer, which is known to accompany the traditional high-temperature nitridation technique. The effective electrical oxide thickness for the devices annealed at 700°C PDA, either with or without LTN treatment, was estimated to be about 2.2 and 2.3 nm, respectively, without considering quantum effects. It was found that the LTN treatment effectively improves the characteristics of the stack gates, such as capacitance-voltage characteristics, frequency dispersion, trap generation rate, and dielectric breakdown voltage even at the high PDA temperature of 700°C.

Reliability for Recessed Channel Structure n-MOSFET

Recessed channel (Rch) structure n-MOSFET has been stressed under hot carrier injected condition and constant voltage stress (CVS). The degraded data are compared with planar channel (Pch) structure. We discuss difference of hot carrier (HC) degradation and oxide lifetime, which can be explained by the electrical field suppression and gate oxide thickness (tox) reduction in recessed channel area.

Thickness determination of thin and ultra-thin SiO 2 films by C-AFM IV-spectroscopy

Conductive atomic force microscopy was used to determine the electrical oxide thickness for five different silicon dioxide layers with thickness in the order of 1.6–5.04 nm. The electrical thickness results were compared with values determined by ellipsometry. A semi-analytical tunnelling current model with one single parameter set was used to superpose current/voltage curves in both the direct tunnelling and the Fowler–Nordheim tunnelling regime regions. The overall electrical oxide thickness was determined by statistical means from results of nearly 3000 IV-curves recorded for different conductive CoCr-coated tips. Good agreement between the shape of model and experimental data was achieved, widely independent of the oxide thickness. Compared with the ellipsometry value, the electrical thickness was larger by a value of 0.36 nm (22%) for the thinnest oxide and smaller by a value of 0.31 nm (6%) for the thickest oxide, while intermediate values yielded differences better than 0.15 nm ( < 6%). The physical differences between the measurement techniques were shown to contribute to this observation. In addition, statistical deviations between single and multiple measurements using a single tip and using a number of different tips were analysed. The causes, for example, natural oxide thickness variations, tip wear, air humidity induced effects and contaminations, are evaluated and discussed. The method proposed was able to determine the electrical oxide thickness with a standard deviation in the order of ± 6–9%. The results suggest that for optimal results it is necessary to perform several repetitions of IV-measurements for one sample and, in addition, to employ more than one tip.