Electrical Oxide Thickness Research Articles

Crystalline zirconia oxide on silicon as alternative gate dielectrics

Epitaxial crystalline yittria-stabilized zirconia (YSZ) oxide films were grown on silicon wafers by the laser molecular beam epitaxy technique. The interface of crystalline YSZ film in contact with silicon was found to be atomically sharp and commensurately crystallized without an amorphous layer. An x-ray photoelectron spectroscopy depth profile and transmission electron microscopy investigation showed that no SiO2 formed at the interface. For a film with electrical equivalent oxide thickness (teox) 14.6 Å, the leakage current is about 1.1×10−3 A/cm2 at 1 V bias voltage. The hysteresis and interface state density in this film are measured to be less than 10 mV and 2.0×1011 eV−1 cm−2, respectively.

Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1/spl times/10/sup 20/ cm/sup -3/ is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented.

A circuit-level perspective of the optimum gate oxide thickness

A performance constrained minimum power-area optimization is introduced to project the physical gate oxide thickness (t/sub ox/) scaling limit from a circuit-level perspective. The circuit optimization is based on the recent physical alpha-power law MOSFET model that enables predictions of CMOS circuit performance for future generations of technology. The model is utilized to derive an equation for propagation delay including the transition time effect. A physical compact gate-tunneling current model is also derived to analyze ultrathin oxide layers. Results indicate that the gate-tunneling power is substantially less (<5%) than the drain-to-source leakage power at the oxide thickness required for optimum CMOS logic circuit performance. As t/sub ox/ is scaled below 3.0 nm, the MOSFET performance improvement resulting from t/sub ox/ scaling diminishes due to an increasing effect of the polysilicon gate depletion depth on the electrical effective oxide thickness. The gate-tunneling power, however, remains exponentially dependent on t/sub ox/, thus resulting in an optimal value of t/sub ox/ where the gate-tunneling power is negligible in comparison to the drain-to-source leakage power. The scaling limit of t/sub ox/ is projected as 2.2, 1.9, and 1.4 nm for the 180, 150, and 100 nm technology generations, respectively.

Plasma processed ultra-thin SiO 2 interfaces for advanced silicon NMOS and PMOS devices: applications to Si-oxide/Si oxynitride, Si-oxide/Si nitride and Si-oxide/transition metal oxide stacked gate dielectrics

The substitution of alternative gate dielectrics for thermally-grown SiO 2 and nitrided SiO 2 in aggressively scaled devices requires a significant processing change in going from thermally-grown to deposited dielectrics. This requires separate and independent steps for (i) the formation of Si-dielectric interface and (ii) the deposition of the dielectric thin film, which can be (a) Si nitride, or a Si oxynitride alloy, or (b) a high- k oxide. It is demonstrated that ultra-thin, nitrided Si–SiO 2 interface layers prepared by 300°C remote plasma processing can be effective in insulating device performance and reliability from deleterious effects associated direct deposition of alternative dielectric materials directly on to hydrogen-terminated Si surfaces. These interfaces perform equally well with Si nitride, Si oxynitride and high- k oxides, and contribute approximately 0.3–0.4 nm to the overall electrical oxide thickness (EOT), limiting aggressive scaling of EOT to approximately 0.6 nm.

Intrinsic limitations on ultimate device performance and reliability at (i) semiconductor–dielectric interfaces and (ii) internal interfaces in stacked dielectrics

The scaling of electrical oxide thickness to 1.0 nm and below for advanced silicon devices requires a change from thermally grown oxides and nitrided oxides to deposited dielectrics which have dielectric constants, k, significantly greater than that of silicon dioxide, k0∼3.8. Implementation of the higher-k dielectrics into field effect transistor devices requires a processing protocol that provides separate and independent control over the properties of the Si–dielectric interface and the bulk dielectric film. Experiments to date have shown that plasma-grown nitrided oxides, ∼0.5–0.6 nm thick, satisfy this requirement. This paper addresses chemical bonding issues at the Si–dielectric interface and at the internal dielectric interface between the plasma-grown nitrided oxides and the high-k alternative dielectrics by applying constraint theory. Si–SiO2 is a prototypical interface between a “rigid” Si substrate and a “floppy” network dielectric, SiO2, and the interfacial properties are modified by a monolayer-scale transition region with excess suboxide bonding over what is required for an ideal interface. Additionally, the defect properties at the internal interface between a nitrided SiO2 interface layer and a bulk dielectric film reflect differences in the average number of bonds/atom, Nav, of the dielectrics on either side of that interface. Experimentally determined interfacial defect concentrations are shown to scale quadratically with increasing differences in Nav thereby establishing a fundamental basis for limitations on device performance and reliability.

Intrinsic limitations on device performance and reliability from bond-constraint induced transition regions at interfaces of stacked dielectrics

The substitution of deposited alternative gate dielectrics for thermally grown SiO2 in aggressively scaled complementary metal–oxide–semiconductor devices requires separate and independent processing steps for (i) the oxidation of the Si substrate to form the Si-dielectric interface and (ii) the deposition of thin film dielectric. Ultrathin plasma-oxidized Si–SiO2 interface layers which contribute approximately 0.3–0.4 nm to the overall electrical oxide thickness have been integrated into devices with Si nitride, Si oxynitride, and Ta2O5 alternative dielectrics. This article proposes an analogy between (i) microscopically inhomogeneous bulk glass alloys such as GeSex with 1&amp;lt;x&amp;lt;2, and (ii) interfaces included in these composite gate dielectric-semiconductor structures including, for examples, the Si–SiO2 and internal dielectric SiO2–Si3N4 interfaces. Scaling relationships for bond defect states applied initially to microscopically inhomogeneous glasses and thin films are applied here to interfaces in stacked gate dielectrics.

An experimental study of the effect of quantization on the effective electrical oxide thickness in MOS electron and hole accumulation layers in heavily doped Si

This work presents for the first time experimental results for the extraction of the increase in the effective electrical oxide thickness (/spl Delta/t/sub ox/=t/sub ox,expt/-t/sub ox,physical/) in MOS accumulation layers with heavily doped substrates due to quantum mechanical (QM) effects, using experimentally measured MOS capacitance-voltage (C-V) characteristics and experimentally verified fullband self-consistent calculations. In addition, the fullband self-consistent simulations have been extended to accumulation regions, and the experimental results for the accumulation region have been compared with simulations. It has been shown that at moderate to high doping levels, /spl Delta/t/sub ox/ is as much as 0.4 to 0.5 nm for both electrons and holes, whereas for very high doping levels (>1/spl times/10/sup 19/ cm/sup -3/) /spl Delta/t/sub ox/ approaches zero. Thus, the experimental accumulation capacitance is predicted sufficiently well by the classical analysis itself.

Characterization of inversion-layer capacitance of holes in Si MOSFET's

Inversion-layer capacitance (C/sub inv/) in p-channel Si MOSFET's is studied experimentally and theoretically with emphasis on the surface carrier concentration (N/sub s/) dependence, which is important in the quantitative description and the physical understanding. The amount of C/sub inv/ and its influence on the gate capacitance are compared between electron and hole inversion layers. It is experimentally verified that, under same physical thickness of gate oxides, the electrical gate oxide thickness, determined from the gate capacitance, is larger for inversion-layer holes than that for inversion-layer electrons, because of smaller values of C/sub inv/ for inversion-layer holes. Self-consistent Poisson-Schrodinger calculation of C/sub inv/ is performed on basis of the approximation of a constant effective mass and is compared with the experimental C/sub inv/. It is found that the calculation using the effective masses at the valence band edge can accurately represent the experimental results over a whole range of N/sub s/.

Modeling and Optimization of Oxynitride Gate Dielectrics Formation by Remote Plasma Nitridation of Silicon Dioxide

The process of remote plasma nitridation of ultrathin gate dielectrics was modeled and optimized using response surface models and physical‐based models. Nitrogen profiles in were obtained by time of flight secondary ion mass spectroscopy (SIMS), and models were developed to predict the total nitrogen dose, top surface nitrogen concentration, and bottom interface nitrogen concentration. Models were also developed to predict the resulting decrease in effective electrical oxide thickness. These models were used for gate dielectric engineering by optimizing the nitrogen profile in dielectric for (i) maximizing the nitrogen concentration at the top surface and the total integrated nitrogen dose (for prevention of boron penetration) and (ii) minimizing nitrogen concentration at the bottom interface (for minimum degradation to metal oxide semiconductor field effect transistor transconductance). © 1999 The Electrochemical Society. All rights reserved.

Process Definition for Obtaining Ultra-Thin Silicon Oxides Using Full-Wafer Electrical and Optical Measurements

ABSTRACTThe objective of this research was to establish a new baseline process for obtaining ultra-thin silicon-oxide gate material in a prototype vertical furnace. Of particular concern was the optimization of a process sequence whereby unpatterned 150 mm diameter wafers ‘see’ the same processing steps prior to gate oxidation as patterned device wafers ‘see’. The figures-of-merit for evaluating process optimization include: i) full-wafer current-voltage (I-V) maps using Hg-gate capacitors; ii) the variation in the current or current density at a given bias voltage, extracted from an I-V map; iii) the variation in electrical oxide thickness that is extracted from full-wafer capacitance-voltage measurements using Hg-gate capacitors; and iv) the variation in optical oxide thickness that is extracted from full-wafer spectroscopic ellipsometry measurements. The results from this research demonstrate that: i) the addition of 1% O2 to the usual N2 gas during the ramp-up cycle in the vertical furnace is necessary to achieve acceptable across-the-wafer oxide-thickness uniformity as determined from both electrical and optical figures-of-merit; and ii) a full-wafer response surface of the current at a given bias voltage is a powerful finger print for process development when the question of variation in as-grown silicon-oxide thickness is at issue.