Efficient VLSI Design Research Articles

A novel approach for design energy efficient inexact reverse carry select adders for IoT applications

Low cost, low form factor and highly energy efficient VLSI design is the key for the success of internet of things (IoT) paradigm. Approximate computing is one of the major techniques used to achieve high performance and energy efficiency in error resistant computationally intense applications. Low power VLSI design is one of the important factors in the designing of new IoT system or reconstructing the existed IoT system. An inexact reverse carry select adder (IRCSLA) with back carry propagation is presented in this work. Three different types of adder implementations were presented in IRCSLA. The method of back carry propagation is applied to the design of both 16-bit ripple carry adder (RCA) & 16-bit carry select adders. These adders were designed in CADENCE schematic tool and simulations were done in Analog Design Environment with 45 nm CMOS technology. The design parameters such as delay and power of the three IRCSLA designs were compared with the existed back carry propagate full adders. IRCSLA-III gives 34.84% reduction in power and 56.91% improvement in delay compared to conventional CSLA adder and also improves the energy at the rate of 86.77% and 71.92% compared to the conventional RCA and a CSLA adder respectively.

IoMT aware data collective quadratic ensembled cat boost module classification algorithm for non-invasive blood glucose monitoring in VLSI design

Internet of Medical Things (IoMT) is the combination of medical devices and utilization by networking technologies. But, the response time and cost were not reduced. In order to address these issues, IoMT Aware Data Collective Quadratic Ensembled Cat Boost Module Classification (IoMT-DCQECBMC) Method is introduced. Initially, IoMT Aware Data Collection is used for gathering data from medical devices. After the data collection process, Quadratic Ensembled Cat Boost Module Classification (QECBM) is carried out in IoMT-DCQECBMC Method to design an efficient VLSI architecture with minimal cost and area. The quadratic classifier is considered the weak learner that categorizes the module for efficient VLSI design. Finally, the weak learners are joined to form the strong classifier to perform non-invasive blood glucose monitoring efficiently. Experimental evaluation is carried out on the factors such as computation cost, area, and accuracy with respect to a number of modules in VLSI circuits. The accuracy of the IoMT-DCQECBMC method is increased by 4% than conventional methods. In addition, the area consumption and computation cost of the proposed IoMT-DCQECBMC method are reduced by 13% to 30% other than existing methods.

Design of Low Power Versatile Bit-Serial Multiplier in Finite Field GF (2m)

Finite field arithmetic is the most important component in applications like cryptography, computer algebra and error correcting codes. Versatility is an important property the hardware industry lacks and trying to establish as much as possible. To survive in this booming technological word, the new designs should be of an adjustable one, which processes the versatile property. In this we have proposed an efficient VLSI design for versatile bit-serial multiplier in finite fields GF (2m). The versatile multiplier designed here modifications done by reducing the unwanted switching activity removed by clock gating scheme. Our design provides a solution to the power reduction. The introduced multiplier operates over a variety of binary fields up to an order of 2m. The value of m can vary up to 264 bits. Multiplier is designed using Verilog HDL.

VLSI Design of a Fast One-Stage Independent Component Extracting System Based on ICA-R Algorithm

Independent component analysis (ICA) is an efficient blind source separation technique, but the extracted independent components are randomly permuted in classic ICA algorithms, and subsequent identification is required to find the desired component. Such a two-stage method causes inefficiency. By utilizing the prior information, ICA with reference (ICA-R) algorithm can extract the desired source signal in one stage without subsequent processing. There are many theoretical extensions on ICA-R, but few hardware implementations can be found. Therefore, the efficient VLSI design of a fast one-stage independent component extracting system based on ICA-R algorithm is presented in this paper. The proposed system consists of Preprocess module and Iteration module, which are designed highly parallel and pipelined to accelerate the extraction process. The designed system is implemented in Kintex-7 FPGA, and its performance is verified using synthesized signal. Experiment results show that the presented system can extract the desired components in one stage without subsequent identification, and the highly parallel circuit structure of the system speeds up the component extracting process by [Formula: see text] compared to software implementation.

An Efficient VLSI Design of AES Cryptography in Memory Implementation

This paper depicts a novel sub bytes strategy for executing the executing the advanced encryption standard (AES) algorithm that offers a considerably enhanced cryptographic strength. Our strategy depends on composite field math randomization, which involves a low cost of execution while not adjusting the algorithm, does not decrease the recurrence of the work and maintains an ideal similarity to the distributed standard. In this document, we suggest a fast and knowledgeable execution of AES in memory (AIM) to scramble the whole part of the memory only when needed. We use NVM’s intrinsic logic working ability to implement the AES algorithm instead of adding extra processing parts to the cost-sensitive memory. The proposed design is implemented using Modelsim 6.4 C and Xilinx tool Verilog HDL and simulated. The proposed framework actualized in FPGA Vertex or Spartan-3.The proposed AES system has been made into an IP and effectively connected in encryption application.

Area-Delay-Energy aware SRAM memory cell and M × N parallel read/write memory array design for quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is an emerging nanotechnology, potentially suitable to replace the popular technologies like Complementary Metal Oxide Semiconductor (CMOS) technology. The evolution of QCA has become prominent due to high operating frequency, nanoscale device and zero current low power nanotechnology. However, the Area-Delay-Energy aware QCA logic circuit design remains a prime concern in this post CMOS technology. In this work the primary attention is given to build efficient QCA circuits. The motivation of this work is to propose Efficient VLSI design in terms of Area, Delay, Power and PDP (Power delay product). Different methodologies are reported to design a combinational and sequential circuit in QCA technology. An extensive focus is given in designing of 3 different QCA based Area-Delay-Energy aware SRAM memory cells, parallel read/write M × N SRAM memory array and peripherals like decoder and multiplexer. Since appropriate signal distribution network (SDN) is an essential aspect to deign QCA circuit, it has also been reported a delay aware signal distribution methodology applicable for any type of QCA logic circuit design. The significant results of this research finding are expressed in terms of Area-Delay-Energy dissipation tradeoff. When compared with respective to the state of art, the performance metric of proposed QCA based memory cells are excelled, on an average 40% reduction in area, 33% and 22% drop in delay and energy dissipation respectively are achieved for proposed three different memory cell design.

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding

Sample adaptive offset (SAO) is a newly introduced in-loop filtering component in H.265/High Efficiency Video Coding (HEVC). While SAO contributes to a notable coding efficiency improvement, the estimation of SAO parameters dominates the complexity of in-loop filtering in HEVC encoding. This paper presents an efficient VLSI design for SAO estimation. Our design features a dual-clock architecture that processes statistics collection (SC) and parameter decision (PD), the two main functional blocks of SAO estimation, at high- and low-speed clocks, respectively. Such a strategy reduces the overall area by 56% by addressing the heterogeneous data flows of SC and PD. To further improve the area and power efficiency, algorithm-architecture co-optimizations are applied, including a coarse range selection (CRS) and an accumulator bit width reduction (ABR). CRS shrinks the range of fine processed bands for the band offset estimation. ABR further reduces the area by narrowing the accumulators of SC. They together achieve another 25% area reduction. The proposed VLSI design is capable of processing 8k at 120-frames/s encoding. It occupies 51k logic gates, only one-third of the circuit area of the state-of-the-art implementations.

Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos

Block-based motion estimation plays a significant role in video codecs by exploiting and reducing the temporal redundancies that exist between consecutive frames in a video sequence. Adaptive Rood Pattern Search (ARPS) is one of the most popular fast motion estimation algorithms. In this paper, VLSI design for the ARPS algorithm is proposed that involves reasonably limited hardware resource without compromising the real-time speed for transmitting HD videos. To tackle the adaptive nature of the algorithm, the proposed design avoids systolic arrays and introduces novel pattern generation methodology that can tackle the adaptive nature of the algorithm. Further, the design incorporates interleaved memory organization with a well–defined sharing strategy to re-use data and ensures high throughput. Working at a frequency of 112MHz, the present design can process 30 Full HD 1080p (1920×1080) frames using only 47.15K gates. Hence, the proposed VLSI architecture can be incorporated in video codecs that can be suitably used in devices like camcorders, tablets and smart phones.

Efficient fuzzy‐controlled and hybrid entropy coding strategy lossless ECG encoder VLSI design for wireless body sensor networks

An efficient VLSI design of a lossless electrocardiogram (ECG) encoder is proposed for wireless body sensor networks. To save wireless transmission power, a novel lossless encoding algorithm had been created for ECG signal compression. The proposed algorithm consists of a novel adaptive predictor based on fuzzy decision control, and a novel hybrid entropy encoder including both a two-stage Huffman and a Golomb-Rice coding. The VLSI architecture contains only 2.71 K gate counts and its core area is 33 929 μm 2 synthesized by a 0.18 μm CMOS process. Moreover, this design can be operated at 100 MHz processing rate by consuming only 30 μW. It achieves an average compression rate of 2.56 for the MIT-BIH arrhythmia database. Compared with previous low-complexity and high-performance lossless ECG encoder studies, this design has a higher compression rate, lower power consumption and lower hardware cost than other VLSI designs.

Implementation and evaluation of a high-performance MIMO detector for wireless LAN systems

This paper presents the implementation and experimental evaluation of an advanced MIMO detector for wireless LAN systems. The proposed detector architecture is based on the well-known lattice-reduction aided MMSE method. Several optimizations at both algorithmic and architectural level are presented which result in an efficient VLSI design able to meet the timing requirements of a practical OFDM-based wireless LAN receiver while keeping complexity at moderate levels. Moreover, the detector offers built-in compensation for transmitter impairments such as nonlinear power amplifier characteristics, hence providing a full and cost-effective solution for practical systems. The described solution is implemented on an FPGA-based IEEE802.11n prototype and evaluation results comparing performance of both conventional MMSE and reduced-lattice detection under several propagation scenarios are presented. Experimental results show significantly lower error rates at the receiver for the advanced detector, or equivalently a lower number of required receiver antenna elements for a given performance target, hence resulting in lower cost, physical size and energy consumption <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

Embedded face recognition based on fast genetic algorithm for intelligent digital photography

In this paper, we propose embedded face recognition (FR) to use in intelligent image system. For efficient FR VLSI design, we use a feature selection and feature extraction method based on Gabor wavelets using a fast genetic algorithm (FGA). Many FR systems are based on Gabor wavelet due to its desirable characteristics of spatial locality and orientation selectivity. However, the process of searching for features with Gabor wavelet is computationally expensive and has an unusual sensibility for variations such as illumination. To overcome these problems and use in real-time applications, we optimize Gabor wavelet's parameters of translation, orientations and scales, which make it approximates a local image contour region by the use of hardware oriented FGA. From experimental results, we certify that our method shows recognition rate of over 97.27 % for FERET dataset, which exceeds the performance of the other popular methods

VLSI design of 1-D DWT architecture with parallel filters

Wavelet transform coding has been drawing much attention because of its ability to decompose images into a hierarchical structure that is suitable for adaptive processing in the transform domain. This paper presents an Efficient VLSI design of one-dimensional direct discrete wavelet transform processor. The proposed architecture computes three DWT stages and uses four parallel filters. The architecture is simple and offers 16-bit precision on input and output data. It is constituted of three basic units: one storage unit, four filters, and a control unit. No memory or registers are used for storing intermediate results. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches. The architecture can compute DWT at a data rate of 7×10 6 samples/s corresponding to a typical clock speed of 7 MHz. The architecture is simulated and verified at the gate level in VLSI. Process parameters used were those of 0.6 μm technology. The chip area is about 15.7 mm 2.

ON THE STUDY OF VLSI DERIVATION FOR OPTICAL FLOW ESTIMATION

In this paper we propose studying several ways to implement a realistic and efficient VLSI design for a gradient-based dense motion estimator. The kind of estimator we focus on belongs to the class of differential methods. It is classically based on the optical flow constraint equation in association with a smoothness regularization term and also incorporates robust cost functions to alleviate the influence of large residuals. This estimator is expressed as the minimization of a global energy function defined within the framework of an incremental formulation associated with a multiresolution setup. In order to make possible the conception of efficient hardware, we consider a modified minimization strategy. This new minimization strategy is not only well suited to VLSI derivation, it is also very efficient in terms of quality of the result. The complete VLSI derivation is realized using high-level specifications.

Area efficient systolic interconnection networks

Area efficient VLSI design of interconnection networks is an important problem in multiprocessor design. In the context of ULSI technology, the delay in signal propagation along wires will become a significant limitation in designing large, fast networks. This limitation is particularly applicable for high wire organisations typically used in interconnection networks. In the paper, it is shown that classical cross-bar type interconnection networks, formed as systolic arrays, have better composite VLSI performance metrics than most popular interconnection networks that use high wire organisations even though systolic organisations have the disadvantage of being larger in terms of silicon area. The authors outline a new, hybrid architecture for interconnection networks that trades speed advantages of systolic arrays with area advantages of high wire organisations. An implementation, in VLSI, of a butterfly network using the proposed approach is described, and it is shown why this is useful in designing an area efficient interconnection network.

A VLSI architecture for computing scale space

Meaningful information about a scene is captured in the intensity changes in an image. These intensity changes occur at various scales depending on their physical origins. Scale-space generated by applying the Laplacian of Gaussian edge detector to the image at a continuum of scales is a powerful representation for detecting and organizing these intensity changes symbolically and has proved to be very useful for one-dimensional signals. The high computational cost of generating scale-space in two dimensions has restricted its use in images. This paper proposes a very efficient single chip VLSI design for scale-space computation in one and two dimensions. The architecture of the chip is based on an algorithm that can provide speeds that are of an order of magnitude higher than the speeds obtainable from other systems proposed in the literature. The design uses the principles of modularity, expandability, and parallelism, and fully utilizes the three properties of Gaussian symmetry, separability, and scaling. Moreover, our proposed algorithm does not approximate the Laplacian of the Gaussian operator; it uses instead four one-dimensional convulations to obtain the computations in two dimensions. The proposed architecture has not been built.

Concurrent Prolog as an Efficient VLSI Design Language

As long as simulation is relied upon, the hardware will only be as good as the test data; therefore most widely used computers contain bugs. Verification is the only known technique for theoretically complete debugging, but it remains impractical despite researchers' efforts. This article explores a methodology in between functional simulation and formal verification. The correctness of hardware is specified as in formal verification. Input and output assertions are given in predicate calculus. Then, instead of showing that output assertions will be satisfied by the functional specification of hardware for all inputs that satisfy input assertions, it is shown that this relation holds for selected inputs. The triple, input assertion, hardware specification, and output assertion are run against test data. The advantage of this method over functional simulation is that the output data are automatically checked for correctness. The advantage over formal verification is that processes can be executed without being penalized by the incompleteness and inefficiency of theorem provers. Concurrent Prolog provides a readable, efficient compromise between functional simulation and formal verification of VLSI chip design. It is well suited for simulation of component systems and may become the language of choice for this application.