Design of Low Power Versatile Bit-Serial Multiplier in Finite Field GF (2m)

Abstract

Finite field arithmetic is the most important component in applications like cryptography, computer algebra and error correcting codes. Versatility is an important property the hardware industry lacks and trying to establish as much as possible. To survive in this booming technological word, the new designs should be of an adjustable one, which processes the versatile property. In this we have proposed an efficient VLSI design for versatile bit-serial multiplier in finite fields GF (2m). The versatile multiplier designed here modifications done by reducing the unwanted switching activity removed by clock gating scheme. Our design provides a solution to the power reduction. The introduced multiplier operates over a variety of binary fields up to an order of 2m. The value of m can vary up to 264 bits. Multiplier is designed using Verilog HDL.