Area efficient systolic interconnection networks

Abstract

Area efficient VLSI design of interconnection networks is an important problem in multiprocessor design. In the context of ULSI technology, the delay in signal propagation along wires will become a significant limitation in designing large, fast networks. This limitation is particularly applicable for high wire organisations typically used in interconnection networks. In the paper, it is shown that classical cross-bar type interconnection networks, formed as systolic arrays, have better composite VLSI performance metrics than most popular interconnection networks that use high wire organisations even though systolic organisations have the disadvantage of being larger in terms of silicon area. The authors outline a new, hybrid architecture for interconnection networks that trades speed advantages of systolic arrays with area advantages of high wire organisations. An implementation, in VLSI, of a butterfly network using the proposed approach is described, and it is shown why this is useful in designing an area efficient interconnection network.