A new power efficient high performance interconnection network for many-core processors

Abstract

Next generation high performance computing will most likely depend on the massively parallel computers. The overall performance of a massively parallel computer system is heavily affected by the interconnection network and its processing nodes. Continuing advances in VLSI technologies promise to deliver more power to individual nodes. However, the on-chip interconnection networks consume up to 50% of the total chip power and off-chip bandwidth is limited to the maximum number of possible out going physical links. In addition, the long wiring and low performance of communication network overwhelm the benefit of parallel computer system whereas it increases total cost. In this paper, we propose a new interconnection network that reduces the problems of high power consumption, long wiring length and low bandwidth issues. We have measured the static network performance and required power consumption of our proposed ‘3D-TESH’ interconnection network and compared the performance with other networks at different levels of hierarchy such as inter-chips, inter-nodes and inter-cabinets. 3D-TESH network has achieved about 52.08% better diameter and about 45.71% better average distance than the 3D-Torus network with 12.61% less router power usage at on-chip level. Furthermore, 3D-TESH requires about 41% less router power usage than 5D-Torus at the on-chip level.