Families of communication architectures for data centers and parallel processing derived by switching network dilation

Abstract

Scientia Iranica D (2016) 23(6), 2891{2897 Sharif University of Technology Scientia Iranica Transactions D: Computer Science & Engineering and Electrical Engineering www.scientiairanica.com Invited Paper Families of communication architectures for data centers and parallel processing derived by switching network dilation B. Parhami Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA 93106-9560, USA. Received 17 April 2016; accepted 17 June 2016 KEYWORDS Abstract. Network dilation is a way of oering system families, at a range of sizes and 1. Introduction introduction of new interconnection networks, while enriching the repertoire of parallel computer designers, also adds to the selection diculty. Interconnection networks can be direct (switches and routers are built into processing nodes) or indirect (a separate switch network connects the processing nodes), with the latter type being more readily scalable and thus preferred in modern parallel computing im- plementations. The optimal interconnection network depends on the volume of data exchange, expected interchange patterns, and, of course, system size. Given that parallel processors are built in a range of sizes constituting system families, it is unreasonable to expect each member of the family to have a separately optimized network that is incompatible with those of other members. Among other diculties, such an Communication; Graph theory; Interconnection network; Parallel processing; Routing algorithm; Symmetric network. computational powers, which share an underlying communication architecture and routing algorithm. We consider indirect networks that connect processing nodes via intermediate switch nodes. In the simplest such indirect networks, there is a switching network of some regular topology, where each switch is connected to d other switches and to exactly one processing node. A variant, which we adopt here because it is more robust in the sense of not losing any processing capability to single-switch failures, is the use of 2-port processing nodes that connect to two neighboring switches. This alternate architecture also has the advantage of increasing the number of processing nodes from n to ( d= 2) n with a factor- of-2 increase in internode distances. A k -dilated version of the latter architecture replaces each processing node with a path network (linear array) of length k , thus growing the network size to k ( d= 2) n and also further increasing internode distances. In this paper, we study topological and performance attributes of such dilated network architectures, proving general theorems about worst-case and average internode distances and deriving the routing algorithm from that of the underlying switch network. © 2016 Sharif University of Technology. All rights reserved. The list of proposed interconnection architectures in parallel and distributed systems is rather extensive, as noted by Duato et al. [1], Haddadi et al. [2], Parhami [3], and Xu [4]. Liszka et al. [5] have observed that comparing such networks with respect to their suitability for a particular application domain is quite challenging, given the multitude of static attributes (diameter, average distance, bisection width, VLSI layout area) and dynamic properties (routing algorithms, deadlock prevention, trac balance, fault tolerance) that must be taken into consideration. Thus, *. Tel.: +1 805 893 3211; Fax: +1 805 893 3262 E-mail address: parhami@ece.ucsb.edu