Scalable crossbar network: a non-blocking interconnection network for large-scale systems

Abstract

Interconnection networks (INs) are used in wide applications of multi-processor systems in order to set up connections between various nodes such as processors and memory modules. However, there is a fundamental problem in INs that has always been considered as one of the most challenging issues in this area. Blocking problem in these networks degrades network performance and consequently the performance of the whole system. In the meantime, the main option for dealing with this problem is the use of non-blocking crossbar networks. However, there are engineering and scaling difficulties when using these networks in large-scale systems. The number of pins on a VLSI chip cannot exceed a few hundreds, which restricts the size of the largest crossbar that should be integrated into a single VLSI chip. Using the idea of multistage implementation of crossbar network can resolve the problem. However, the next problem that arises with this idea is high hardware cost. Therefore, in this paper, a new implementation of crossbar network named scalable crossbar network (SCN) that is a non-blocking network is presented to cope with the aforementioned scaling problems. In addition, performance analysis results show that SCN outperforms multistage crossbar networks and multistage interconnection networks in terms of terminal reliability, mean time to failure, and system failure rate.