Efficient Circuit Simulation Research Articles

Efficient Quantum Circuit Simulation by Tensor Network Methods on Modern GPUs

Efficient simulation of quantum circuits has become indispensable with the rapid development of quantum hardware. The primary simulation methods are based on state vectors and tensor networks. As the number of qubits and quantum gates grows larger in current quantum devices, traditional state-vector based quantum circuit simulation methods prove inadequate due to the overwhelming size of the Hilbert space and extensive entanglement. Consequently, brutal force tensor network simulation algorithms become the only viable solution in such scenarios. The two main challenges faced in tensor network simulation algorithms are optimal contraction path finding and efficient execution on modern computing devices, with the latter determines the actual efficiency. In this study, we investigate the optimization of such tensor network simulations on modern GPUs and propose general optimization strategies from two aspects: computational efficiency and accuracy. Firstly, we propose to transform critical Einstein summation operations into GEMM operations, leveraging the specific features of tensor network simulations to amplify the efficiency of GPUs. Secondly, by analyzing the data characteristics of quantum circuits, we employ extended precision to ensure the accuracy of simulation results and mixed precision to fully exploit the potential of GPUs, resulting in faster and more precise simulations. Our numerical experiments demonstrate that our approach can achieve a 3.96x reduction in verification time for random quantum circuit samples in the 18-cycle case of Sycamore, with sustained performance exceeding 21 TFLOPS on one A100. This method can be easily extended to the 20-cycle case, maintaining the same performance, accelerating by 12.5x compared to the state-of-the-art CPU-based results and 4.48-6.78x compared to the state-of-the-art GPU-based results reported in the literature. Furthermore, the strategies presented in this article hold general applicability for accelerating problems that can be tackled by contracting tensor networks such as graphical models and combinatorial optimizations.

Efficient classical simulation of cluster state quantum circuits with alternative inputs

We provide new examples of pure entangled systems related to cluster state quantum computation that can be efficiently simulated classically. In cluster state quantum computation input qubits are initialised in the `equator' of the Bloch sphere, CZ gates are applied, and finally the qubits are measured adaptively using Z measurements or measurements of cos⁡(θ)X+sin⁡(θ)Y operators. We consider what happens when the initialisation step is modified, and show that for lattices of finite degree D, there is a constant λ≈2.06 such that if the qubits are prepared in a state that is within λ−D in trace distance of a state that is diagonal in the computational basis, then the system can be efficiently simulated classically in the sense of sampling from the output distribution within a desired total variation distance. In the square lattice with D=4 for instance, λ−D≈0.056. We develop a coarse grained version of the argument which increases the size of the classically efficient region. In the case of the square lattice of qubits, the size of the classically simulatable region increases in size to at least around ≈0.070, and in fact probably increases to around ≈0.1. The results generalise to a broader family of systems, including qudit systems where the interaction is diagonal in the computational basis and the measurements are either in the computational basis or unbiased to it. Potential readers who only want the short version can get much of the intuition from figures 1 to 3.

A transistor model for the cystic fibrosis transmembrane conductance regulator

In this paper we present a transistor circuit model for cystic fibrosis transmembrane conductance regulator (CFTR) that seeks to map the functional form of CFTR both in wild type and mutants. The circuit architecture is configured so that the function, and as much as possible the form, faithfully represents what is known about CFTR from cryo-electron microscopy and molecular dynamics. The model is a mixed analog-digital topology with an AND gate receiving the input from two separate ATP-nucleotide-binding domain binding events. The analog portion of the circuit takes the output from the AND gate as its input. The input to the circuit model and its noise characteristics are extracted from single-channel patch-clamp experiments. The chloride current predicted by the model is then compared with single-channel patch-clamp recordings for wild-type CFTR. We also consider the patch-clamp recordings from CFTR with a G551D point mutation, a clinically relevant mutant that is responsive to therapeutic management. Our circuit model approach enables bioengineering approaches to CFTR and allows biophysicists to use efficient circuit simulation tools to analyze its behavior.

Simulation of Switched-Mode Power Conversion Circuits With Extended Impedance Method

Efficient simulation of switched-mode power conversion circuits is necessary for the analysis and optimization of power electronics. This paper introduces the extended impedance method (EIM) to the simulation and analysis of general switched-mode power converter circuits. By using the EIM method, the conventional impedance concept can be extended to involve more linear time-variant (LTV) and nonlinear devices, such as MOSFET switches and diodes, which are commonly used in switched-mode power conversion circuits. EIM models a circuit network from the component level in the frequency domain, rather than from the system-level constitutive differential equation in the time domain. Compared with the conventional averaging method, EIM can reveal more high-frequency features of a switched-mode converter circuit, in particular, those around the switching instants. A buck converter is taken as a representative example to validate the EIM based analysis. Both the simulation and experimental results prove that EIM provides precise numerical results, which match the real waveform, as the commercial simulators, e.g. PSpice and ADS, do. Moreover, it largely reduces the computational complexity towards more efficient and more flexible steady-state analysis of switched-mode power electronics.

Deflated Restarting of Exponential Integrator Method with an Implicit Regularization for Efficient Transient Circuit Simulation

Exponential integrator (EI) method based on Krylov subspace approximation is a promising method for large-scale transient circuit simulation. However, it suffers from the singularity problem and consumes large subspace dimensions for stiff circuits when using the ordinary Krylov subspace. Restarting schemes are commonly applied to reduce the subspace dimension, but they also slow down the convergence and degrade the overall computational efficiency. In this paper, we first devise an implicit and sparsity-preserving regularization technique to tackle the singularity problem facing EI in the ordinary Krylov subspace framework. Next, we analyze the root cause of the slow convergence of the ordinary Krylov subspace methods when applied to stiff circuits. Based on the analysis, we propose a deflated restarting scheme, compatible with the above regularization technique, to accelerate the convergence of restarted Krylov subspace approximation for EI methods. Numerical experiments demonstrate the effectiveness of the proposed regularization technique, and up to 50% convergence improvements for Krylov subspace approximation compared to the non-deflated version.

Resilience of Quantum Random Access Memory to Generic Noise

Quantum random access memory (QRAM)—memory which stores classical data but allows queries to be performed in superposition—is required for the implementation of numerous quantum algorithms. While naive implementations of QRAM are highly susceptible to decoherence and hence not scalable, it has been argued that the bucket-brigade QRAM architecture [Giovannetti et al., Phys. Rev. Lett. 100, 160501 (2008)] is highly resilient to noise, with the infidelity of a query scaling only logarithmically with the memory size. In prior analyses, however, this favorable scaling followed directly from the use of contrived noise models, thus leaving open the question of whether experimental implementations would actually enjoy the purported scaling advantage. In this work, we study the effects of decoherence on QRAM in full generality. Our main result is a proof that this favorable infidelity scaling holds for arbitrary error channels (including, e.g., depolarizing noise and coherent errors). Our proof identifies the origin of this noise resilience as the limited entanglement among the memory’s components, and it also reveals that significant architectural simplifications can be made while preserving the noise resilience. We verify these results numerically using a novel classical algorithm for the efficient simulation of noisy QRAM circuits. Our findings indicate that QRAM can be implemented with existing hardware in realistically noisy devices, and that high-fidelity queries are possible without quantum error correction. Furthermore, we also prove that the benefits of the bucket-brigade architecture persist when quantum error correction is used, in which case the scheme offers improved hardware efficiency and resilience to logical errors.4 MoreReceived 21 December 2020Accepted 13 April 2021DOI:https://doi.org/10.1103/PRXQuantum.2.020311Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.Published by the American Physical SocietyPhysics Subject Headings (PhySH)Research AreasQuantum algorithmsQuantum computationQuantum information architectures & platformsQuantum information processingQuantum Information

Simple heuristics for efficient parallel tensor contraction and quantum circuit simulation

Tensor networks are the main building blocks in a wide variety of computational sciences, ranging from many-body theory and quantum computing to probability and machine learning. Here we propose a parallel algorithm for the contraction of tensor networks using probabilistic graphical models. Our approach is based on the heuristic solution of the $\mu$-treewidth deletion problem in graph theory. We apply the resulting algorithm to the simulation of random quantum circuits and discuss the extensions for general tensor network contractions.

On the usage of a time-frequency switch mode algorithm to efficiently simulate RF circuits

Wireless devices integrating more and more features in ever-smaller packages have become integral part of everyone’s daily life. These systems have seen a continuous push to profit from digital signal processing techniques, in which signals are no longer traditional continuous amplitude and/or phase-modulated carriers, but became pulsed waveforms where the amplitude and/or phase are coded in some on–off digital scheme. This on–off scenario has been addressing new challenges to the circuit-level simulation of such systems. Having this in mind this paper aims to propose an innovative time–frequency simulation technique based on a switch mode algorithm, which is specially conceived for the efficient numerical simulation of RF circuits whose stimuli are intermittently turned on and off for unknown periods of time. At present, to simulate this category of circuits commercial tools have no choice than to make use of full conventional SPICE algorithms. This paper suggests an alternative way, which can result in significant speedups, without perceptible loss in accuracy.

On the efficient simulation of electrical circuits with constant phase elements: The Warburg element as a test case

SummaryThe constant phase Element (CPE) concept naturally emerges as a model for describing a range of electrical phenomena where ionic diffusion is involved. We suggest a new method for modelling the transient behavior of electrical circuits that contain CPE elements. Without loss of generality, we study the Warburg element to demonstrate the method, but the method can be easily extended to any CPE. Transient simulations of such elements require the numerical evaluation of a computationally expensive convolution integral that links the voltage drop across the element, with the current that passed through it. In our work we suggest a new method for reducing the computational cost of the numerical evaluation of the convolution integral. We show that the computational cost can be reduced by one order of magnitude.

Basker: Parallel sparse LU factorization utilizing hierarchical parallelism and data layouts

Abstract Transient simulation in circuit simulation tools, such as SPICE and Xyce, depend on scalable and robust sparse LU factorizations for efficient numerical simulation of circuits and power grids. As the need for simulations of very large circuits grow, the prevalence of multicore architectures enable us to use shared memory parallel algorithms for such simulations. A parallel factorization is a critical component of such shared memory parallel simulations. We develop a parallel sparse factorization algorithm that can solve problems from circuit simulations efficiently, and map well to architectural features. This new factorization algorithm exposes hierarchical parallelism to accommodate irregular structure that arise in our target problems. It also uses a hierarchical two-dimensional data layout which reduces synchronization costs and maps to memory hierarchy found in multicore processors. We present an OpenMP based implementation of the parallel algorithm in a new multithreaded solver called Basker in the Trilinos framework. We present performance evaluations of Basker on the Intel SandyBridge and Xeon Phi platforms using circuit and power grid matrices taken from the University of Florida sparse matrix collection and from Xyce circuit simulation. Basker achieves a geometric mean speedup of 5.91× on CPU (16 cores) and 7.4× on Xeon Phi (32 cores) relative to state-of-the-art solver KLU. Basker outperforms Intel MKL Pardiso solver (PMKL) by as much as 30× on CPU (16 cores) and 7.5× on Xeon Phi (32 cores) for low fill-in circuit matrices. Furthermore, Basker provides 5.4× speedup on a challenging matrix sequence taken from an actual Xyce simulation.

Efficient classical simulation of matchgate circuits with generalized inputs and measurements

Matchgates are a restricted set of two-qubit gates known to be classically simulable under particular conditions. Specifically, if a circuit consists only of nearest-neighbour matchgates, an efficient classical simulation is possible if either (i) the input is a computational basis state and the simulation requires computing probabilities of multi-qubit outcomes (including also adaptive measurements), or (ii) if the input is an arbitrary product state, but the output of the circuit consists of a single qubit. In this paper we extend these results to show that matchgates are classically simulable even in the most general combination of these settings, namely, if the inputs are arbitrary product states, if the measurements are over arbitrarily many output qubits, and if adaptive measurements are allowed. This remains true even for arbitrary single-qubit measurements, albeit only in a weaker notion of classical simulation. These results make for an interesting contrast with other restricted models of computation, such as Clifford circuits or (bosonic) linear optics, where the complexity of simulation varies greatly under similar modifications.

Model Reduction and Simulation of Nonlinear Circuits via Tensor Decomposition

Model order reduction of nonlinear circuits (especially highly nonlinear circuits) has always been a theoretically and numerically challenging task. In this paper, we utilize tensors (namely, a higher order generalization of matrices) to develop a tensor-based nonlinear model order reduction algorithm we named TNMOR for the efficient simulation of nonlinear circuits. Unlike existing nonlinear model order reduction methods, in TNMOR high-order nonlinearities are captured using tensors, followed by decomposition and reduction to a compact tensor-based reduced-order model. Therefore, TNMOR completely avoids the dense reduced-order system matrices, which in turn allows faster simulation and a smaller memory requirement if relatively low-rank approximations of these tensors exist. Numerical experiments on transient and periodic steady-state analyses confirm the superior accuracy and efficiency of TNMOR, particularly in highly nonlinear scenarios.

A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits

To explore single-electron circuits for different applications, a proper simulation platform where circuits consisting of single electron transistors and other devices can be simulated efficiently is needed. A macro model of single electron transistor featuring symmetric tunnel junctions is proposed. In the proposed model, a voltage controlled current source is incorporated in the existing model of SET to get more accurate results. Three scaling factors have been included in the model to improve the versatility of the model. The advantages and disadvantages of different simulation methods are discussed as a justification for choosing the macro model approach. The proposed model can efficiently describe the physical phenomena occurring in coulomb blockade and coulomb oscillation regions. The SPICE environment is used for the simulation and to verify the accuracy, the model is applied to a single electron inverter circuit and the effect of macro model parameters on the noise margin is investigated to estimate the robustness of the inverter cell. A multi peak negative differential resistance circuit based on the proposed macro model is designed and demonstrated. Also, an integrator circuit has been designed to prove the validity of the proposed model in the analog domain. Further, the linearity of the integrator circuit is analyzed through harmonic and intermodulation distortion analysis.

Optimal frequency sweep method in multi-rate circuit simulation

Purpose – Radio-frequency circuits often possess a multi-rate behavior. Slow changing baseband signals and fast oscillating carrier signals often occur in the same circuit. Frequency modulated signals pose a particular challenge. The paper aims to discuss these issues. Design/methodology/approach – The ordinary circuit differential equations are first rewritten by a system of (multi-rate) partial differential equations in order to decouple the different time scales. For an efficient simulation the paper needs an optimal choice of a frequency-dependent parameter. This is achieved by an additional smoothness condition. Findings – By incorporating the smoothness condition into the discretization, the paper obtains a non-linear system of equations complemented by a minimization constraint. This problem is solved by a modified Newton method, which needs only little extra computational effort. The method is tested on a phase locked loop with a frequency modulated input signal. Originality/value – A new optimal frequency sweep method was introduced, which will permit a very efficient simulation of multi-rate circuits.

Parallel Simulation of Large Linear Circuits With Nonlinear Terminations Using High-Order Stable Methods

To meet the growing demand for efficient circuit simulation tools, Obreshkov formula (ObF)-based high-order integration methods were recently proposed. However, one of the challenges in this method is the growing computational cost of the solution at a particular time point with the increasing orders of the ObF. To address this issue and target high-speed circuits with large linear blocks and nonlinear loads, a new parallel framework is proposed in this paper to minimize the CPU time associated with the solution at any time point. For this purpose, recently identified special properties of the resulting circuit matrices and the node-tearing principles are exploited, while developing an efficient parallel simulation framework. Numerical examples are presented to demonstrate the validity and efficiency of the proposed parallel method.

Continuity equation based nonquasi-static charge model for independent double gate MOSFET

Using the numerical device simulation we show that the relationship between the surface potentials along the channel in any double gate (DG) MOSFET remains invariant in QS (quasistatic) and NQS (nonquasi-static) condition for the same terminal voltages. This concept along with the recently proposed `piecewise charge linearization' technique is then used to develop the intrinsic NQS charge model for a Independent DG (IDG) MOSFET by solving the governing continuity equation. It is also demonstrated that unlike the usual MOSFET transcapacitances, the inter-gate transcapacitance of a IDG-MOSFET initially increases with the frequency and then saturates, which might find novel analog circuit application. The proposed NQS model shows good agreement with numerical device simulations and appears to be useful for efficient circuit simulation.

Nonquasi-Static Charge Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry

With the unique quasi-linear relationship between the surface potentials along the channel, recently we have proposed a quasi-static terminal charge model for common double-gate MOSFETs, which might have asymmetric gate oxide thickness. In this brief, we extend this concept to develop the nonquasi-static (NQS) charge model for the same by solving the governing continuity equations. The proposed NQS model shows good agreement against TCAD simulations and appears to be useful for efficient circuit simulation.

Approximation of realistic errors by Clifford channels and Pauli measurements

The Gottesman-Knill theorem allows for the efficient simulation of stabilizer-based quantum error-correction circuits. Errors in these circuits are commonly modeled as depolarizing channels by using Monte Carlo methods to insert Pauli gates randomly throughout the circuit. Although convenient, these channels are poor approximations of common, realistic channels such as amplitude damping. Here we analyze a larger set of efficiently simulable error channels by allowing the random insertion of any one-qubit gate or measurement that can be efficiently simulated within the stabilizer formalism. Our error channels are shown to be a viable method for accurately approximating realistic error channels.

A Computationally Efficient Technique for Prototyping Planar Antennas and Printed Circuits for Wireless Applications

In this paper, we present a novel procedure for an efficient and accurate electromagnetic simulation of microstrip circuits and printed antennas etched in layered media. The proposed approach, based on a new algorithm referred to herein as the equivalent medium approach (EMA), is applied for a rapid design of the preliminary desired circuit prototype. The illustrated technique yields reliable results and reduces the computational time in comparison with the conventional method of moments (MoM). Some examples that demonstrate the accuracy and the efficiency of the described procedure are included.

Parallel circuit simulation with adaptively controlled projective integration

In this article, a parallel transient circuit simulation approach based on an adaptively-controlled time-stepping scheme is proposed. Different from the widely-used implicit numerical integration techniques in most transient simulators, this work exploits the recently-developed explicit telescopic projective numerical integration method for efficient parallel circuit simulation. Because telescopic projective integration addresses the well-known stability issue of explicit numerical integrations by adopting combinations of inner integrators and outer integrators in a multilevel fashion, the simulation time-step is no longer limited by the smallest time constant in the circuit. With dynamic control of telescopic projective integration, the proposed projective integration framework not only leads to noticeable efficiency improvement in circuit simulation, it also lends itself to straightforward parallelization due to its explicit nature. The latter has led to encouraging runtime efficiencies, observed on shared-memory parallel platforms. In addition to solving standard initial-value problems (IVPs) of differential equations, the same telescopic integration framework is adopted for solving final-value problems (FVPs), where the system is integrated backwards in time. Through a new elegant formulation, we show how an IVP and FVP can be simultaneously solved to allow for a coarse-grained bidirectional parallel circuit simulation scheme. Such a bidirectional approach is demonstrated in the context of parallel shooting-Newton-based steady-state circuit analysis. The proposed bidirectional approach has unique and favorable properties: the solutions of the two ODE problems are completely data-independent with built-in automatic load balancing.