Efficient Error Detection Research Articles

Simultaneous Fault Models for the Generation and Location of Efficient Error Detection Mechanisms

Abstract The application of machine learning to software fault injection data has been shown to be an effective approach for the generation of efficient error detection mechanisms (EDMs). However, such approaches to the design of EDMs have invariably adopted a fault model with a single-fault assumption, limiting the relevance of the detectors and their evaluation. Software containing more than a single fault is commonplace, with safety standards recognizing that critical failures are often the result of unlikely or unforeseen combinations of faults. This paper addresses this shortcoming, demonstrating that it is possible to generate efficient EDMs under simultaneous fault models. In particular, it is shown that (i) efficient EDMs can be designed using fault injection data collected under models accounting for the occurrence of simultaneous faults, (ii) exhaustive fault injection under a simultaneous bit flip model can yield improved EDM efficiency, (iii) exhaustive fault injection under a simultaneous bit flip model can be made non-exhaustive and (iv) EDMs can be relocated within a software system using program slicing, reducing the resource costs of experimentation to practicable levels without sacrificing EDM efficiency.

Efficient error detection and correction method for 1-out-of-3 binary signed digit adders

ABSTRACTBinary Signed Digit (BSD) number system has been extensively used in high-speed applications due to taking carry-free adders and high-speed multipliers. The 1-out-of-3 BSD encoding is an inherently fault-tolerant BSD encoding, which is a subset of m-out-of-n codes widely employed for error detection and correction. Although some fault-tolerant methods have been already proposed for 1-out-of-3 BSD adder, an efficient structure with both capabilities of fault detection and correction has not been introduced yet. In this paper, a 1-out-of-3 BSD adder with error detection and correction capabilities is presented. In spite of the negligible penalties in delay, power consumption, and area overhead, synthesis results show that more fault tolerance capability is achieved by the proposed method.

Commissioning and Evaluation of an Electronic Portal Imaging Device-Based In-Vivo Dosimetry Software.

This study reports on our experience with the in-vivo dose verification software, EPIgray® (DOSIsoft, Cachan, France). After the initial commissioning process, clinical experiments on phantom treatments were evaluated to assess the level of accuracy of the electronic portal imaging device (EPID) based in-vivo dose verification.EPIgray was commissioned based on the company’s instructions. This involved ion chamber measurements and portal imaging of solid water blocks of various thicknesses between 5 and 35 cm. Field sizes varied between 2 x 2 cm2 and 20 x 20 cm2. The determined conversion factors were adjusted through an additional iterative process using treatment planning system calculations. Subsequently, evaluation was performed using treatment plans of single and opposed beams, as well as intensity modulated radiotherapy (IMRT) plans, based on recommendations from the task group report TG-119 to test for dose reconstruction accuracy. All tests were performed using blocks of solid water slabs as a phantom.For single square fields, the dose at isocenter was reconstructed within 3% accuracy in EPIgray compared to the treatment planning system dose. Similarly, the relative deviation of the total dose was accurately reconstructed within 3% for all IMRT plans with points placed inside a high-dose region near the isocenter. Predictions became less accurate than < 5% when the evaluation point was outside the treatment target. Dose at points 5 cm or more away from the isocenter or within an avoidance structure was reconstructed less reliably.EPIgray formalism accuracy is adequate for an efficient error detection system with verifications performed in high-dose volumes. It provides immediate intra-fractional feedback on the delivery of treatment plans without affecting the treatment beam. Besides the EPID, no additional hardware is required. The software evaluates local point dose measurements to verify treatment plan delivery and patient positioning within 5% accuracy, depending on the placement of evaluation points.

Efficient and Reliable Error Detection Architectures of Hash-Counter-Hash Tweakable Enciphering Schemes

Through pseudorandom permutation, tweakable enciphering schemes (TES) constitute block cipher modes of operation which perform length-preserving computations. The state-of-the-art research has focused on different aspects of TES, including implementations on hardware [field-programmable gate array (FPGA)/ application-specific integrated circuit (ASIC)] and software (hard/soft-core microcontrollers) platforms, algorithmic security, and applicability to sensitive, security-constrained usage models. In this article, we propose efficient approaches for protecting such schemes against natural and malicious faults. Specifically, noting that intelligent attackers do not merely get confined to injecting multiple faults, one major benchmark for the proposed schemes is evaluation toward biased and burst fault models. We evaluate a variant of TES, i.e., the Hash-Counter-Hash scheme, which involves polynomial hashing as other variants are either similar or do not constitute finite field multiplication which, by far, is the most involved operation in TES. In addition, we benchmark the overhead and performance degradation on the ASIC platform. The results of our error injection simulations and ASIC implementations show the suitability of the proposed approaches for a wide range of applications including deeply embedded systems.

Children’s Performance Estimation in Mathematics and Science Tests over a School Year: A Pilot Study

Introduction. The metacognitve ability to accurately estimate ones performance in a test, is assumed to be of central importance for initializing task-oriented effort. In addition activating adequate problem-solving strategies, and engaging in efficient error detection and correction. Although school children’s’ ability to estimate their own performance has been widely investigated, this was mostly done under highly-controlled, experimental set-ups including only one single test occasion.Method. The aim of this study was to investigate this metacognitive ability in the context of real achievement tests in mathematics. Developed and applied by a teacher of a 5th grade class over the course of a school year these tests allowed the exploration of the variability of performance estimation accuracy as a function of test difficulty.Results. Mean performance estimations were generally close to actual performance with somewhat less variability compared to test performance. When grouping the children into three achievement levels, results revealed higher accuracy of performance estimations in the high achievers compared to the low and average achievers. In order to explore the generalization of these findings, analyses were also conducted for the same children’s tests in their science classes revealing a very similar pattern of results compared to the domain of mathematics.Discussion and Conclusion. By and large, the present study, in a natural environment, confirmed previous laboratory findings but also offered additional insights into the generalisation and the test dependency of students’ performances estimations.

Children's performance estimation in mathematics and science tests over a school year: A pilot study

The metacognitve ability to accurately estimate ones performance in a test, is assumed to be of central importance for initializing task-oriented effort. In addition activating adequate problem-solving strategies, and engaging in efficient error detection and correction. Although school children's' ability to estimate their own performance has been widely investigated, this was mostly done under highly-controlled, experimental set-ups including only one single test occasion. Method: The aim of this study was to investigate this metacognitive ability in the context of real achievement tests in mathematics. Developed and applied by a teacher of a 5th grade class over the course of a school year these tests allowed the exploration of the variability of performance estimation accuracy as a function of test difficulty. Results: Mean performance estimations were generally close to actual performance with somewhat less variability compared to test performance. When grouping the children into three achievement levels, results revealed higher accuracy of performance estimations in the high achievers compared to the low and average achievers. In order to explore the generalization of these findings, analyses were also conducted for the same children's tests in their science classes revealing a very similar pattern of results compared to the domain of mathematics. Discussion and Conclusion: By and large, the present study, in a natural environment, confirmed previous laboratory findings but also offered additional insights into the generalisation and the test dependency of students' performances estimations.

Fault Attacks Resistant Architecture for KECCAK Hash Function

The KECCAK cryptographic algorithms widely used in embedded circuits to ensure a high level of security to any systems which require hashing as the integrity checking and random number generation. One of the most efficient cryptanalysis techniques against KECCAK implementation is the fault injection attacks. Until now, only a few fault detection schemes for KECCAK have been presented. In this paper, in order to provide a high level of security against fault attacks, an efficient error detection scheme based on scrambling technique has been proposed. To evaluate the robust of the proposed detection scheme against faults attacks, we perform fault injection simulations and we show that the fault coverage is about 99,996%. We have described the proposed detection scheme and through the Field-Programmable Gate Array analysis, results show that the proposed scheme can be easily implemented with low complexity and can efficiently protect KECCAK against fault attacks. Moreover, the Field-Programmable Gate Array implementation results show that the proposed KECCAK fault detection scheme realises a compromise between implementation cost and KECCAK robustness against fault attacks.

Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA

The Viterbi algorithm is commonly applied to a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this paper, efficient error detection schemes for architectures based on low-latency, low-complexity Viterbi decoders are presented. The merit of the proposed schemes is that reliability requirements, overhead tolerance, and performance degradation limits are embedded in the structures and can be adapted accordingly. We also present three variants of recomputing with encoded operands and its modifications to detect both transient and permanent faults, coupled with signature-based schemes. The instrumented decoder architecture has been subjected to extensive error detection assessments through simulations, and application-specific integrated circuit (ASIC) [32 nm library] and field-programmable gate array (FPGA) [Xilinx Virtex-6 family] implementations for benchmark. The proposed fine-grained approaches can be utilized based on reliability objectives and performance/implementation metrics degradation tolerance.

Reliable Hardware Architectures for Cryptographic Block Ciphers LED and HIGHT

Cryptographic architectures provide different security properties to sensitive usage models. However, unless reliability of architectures is guaranteed, such security properties can be undermined through natural or malicious faults. In this paper, two underlying block ciphers which can be used in authenticated encryption algorithms are considered, i.e., light encryption device and high security and lightweight block ciphers. The former is of the Advanced Encryption Standard type and has been considered area-efficient, while the latter constitutes a Feistel network structure and is suitable for low-complexity and low-power embedded security applications. In this paper, we propose efficient error detection architectures including variants of recomputing with encoded operands and signature-based schemes to detect both transient and permanent faults. Authenticated encryption is applied in cryptography to provide confidentiality, integrity, and authenticity simultaneously to the message sent in a communication channel. In this paper, we show that the proposed schemes are applicable to the case study of simple lightweight CFB for providing authenticated encryption with associated data. The error simulations are performed using Xilinx Integrated Synthesis Environment tool and the results are benchmarked for the Xilinx FPGA family Virtex-7 to assess the reliability capability and efficiency of the proposed architectures.

Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands

A variable latency adder (VLA) reduces average addition time by using speculation: the exact arithmetic function is replaced by an approximated one, that is faster and gives correct results most of the times. When speculation fails, an error detection and correction circuit gives the correct result in the following clock cycle. Previous papers investigate VLAs based on Kogge-Stone, Han-Carlson or carry select topologies, speculating that carry propagation involves only a few consecutive bits. In several applications using 2's complement representation, however, operands have a Gaussian distribution and a nontrivial portion of carry chains can be as long as the adder size. In this paper we propose five novel VLA architectures, based on Brent-Kung, Ladner-Fisher, Sklansky, Hybrid Han-Carlson, and Carry increment parallel-prefix topologies. Moreover, we present a new efficient error detection and correction technique, that makes proposed VLAs suitable for applications using 2's complement representation. In order to investigate VLAs performances, proposed architectures have been synthesized using the UMC 65 nm library, for operand lengths ranging from 32 to 128 bits. Obtained results show that proposed VLAs outperform previous speculative architectures and standard (non-speculative) adders when high-speed is required.

SU-G-BRB-06: Commissioning and Evaluation of EPID-Based in Vivo Dosimetry Software Using a Tissue-Maximum Ratio Approach

Purpose: To commission and evaluate an in vivo EPID-based transit dosimetry software (EPIgray, DOSIsoft, Cachan, France) using simple fields and TG119-based IMRT treatment plans. Methods: EPIgray was commissioned on a Truebeam based on finite tissue-maximum ratio (fTMR) measurements with solid water blocks of thicknesses between 0 and 37 cm. Field sizes varied from 2×2 to 20×20 cm2. Subsequently, treatment plans of single and opposed beams with field sizes between 4×4 and 15×15 cm2 as well as IMRT plans were measured to evaluate the dose reconstruction accuracy. Single field dose predictions were made for anterior-posterior and lateral beams. IMRT plans were created based on TG119 recommendations. The reconstructed dose was compared to the planned dose for selected points at isocenter and away from isocenter. Results: For single square fields, the dose in EPIgray was reconstructed within 3% accuracy at isocenter relative to the planned dose. Similarly, the relative deviation of the total dose was accurately reconstructed within 3% for all IMRT plans with points placed inside a high dose region near the isocenter. Predictions became less accurate than 5% when the evaluation point was outside the majority of IMRT beam segments. Additionally, points 5 cm or more away from the isocenter or within an avoidance structure were predicted less reliably. Conclusion: EPIgray formalism accuracy is adequate for an efficient error detection system. It provides immediate intra-fractional feedback on the delivery of treatment plans without affecting the treatment beam. Besides the EPID, no additional hardware is required, which makes it accessible to all clinics. The software evaluates point dose measurements to verify treatment plan delivery and patient positioning within 5% accuracy, depending on the placement of evaluation points. EPIgray is not intended to replace patient-specific quality assurance but should be utilized as an additional layer of safety for continuous patient treatment verification. This research is supported by DOSIsoft.

Improvement of the Error-detection Mechanism in Adults with Dyslexia Following Reading Acceleration Training.

The error-detection mechanism aids in preventing error repetition during a given task. Electroencephalography demonstrates that error detection involves two event-related potential components: error-related and correct-response negativities (ERN and CRN, respectively). Dyslexia is characterized by slow, inaccurate reading. In particular, individuals with dyslexia have a less active error-detection mechanism during reading than typical readers. In the current study, we examined whether a reading training programme could improve the ability to recognize words automatically (lexical representations) in adults with dyslexia, thereby resulting in more efficient error detection during reading. Behavioural and electrophysiological measures were obtained using a lexical decision task before and after participants trained with the reading acceleration programme. ERN amplitudes were smaller in individuals with dyslexia than in typical readers before training but increased following training, as did behavioural reading scores. Differences between the pre-training and post-training ERN and CRN components were larger in individuals with dyslexia than in typical readers. Also, the error-detection mechanism as represented by the ERN/CRN complex might serve as a biomarker for dyslexia and be used to evaluate the effectiveness of reading intervention programmes. Copyright © 2016 John Wiley & Sons, Ltd.

A generic buffer occupancy expression for stop-and-wait hybrid automatic repeat request protocol over unstable channels

Recently, there has been a rapid progress in the field of wireless networks and mobile communications which makes the constraints on the used links clearly unconcealed. Wireless links are characterized by limited bandwidth and high latencies. Moreover, the bit-error-rate (BER) is very high in such environments for various reasons out of which weather conditions, cross-link interference, and mobility. High BER causes corruption in the data being transmitted over these channels. Therefore, convolutional encoding has been originated to be a professional means of communication over noisy environments. Sequential decoding, a category of convolutional codes, represents an efficient error detection and correction mechanism which attracts the attention for most of current researchers as for having a complexity that is dependent to the channel condition. In this paper, we propose a new queuing study over networking systems that make use of sequential decoders. Hence, the adopted flow and error control refer to stop-and-wait hybrid automatic repeat request. However, our queuing study is a novel extension to our prior work in which the lowest decoding complexity was fixed and did not account for the channel state. In other words, our proposed closed-form expression of the average buffer occupancy is totally generic and parameterized by not only channel condition and packet incoming rate, but also those that are automatically adapted to the channel conditions which include lower and upper bound decoding limits.

Differential analysis of Operating System indicators for anomaly detection in dependable systems: An experimental study

Dependable complex systems often operate under variable and non-stationary conditions, which requires efficient and extensive monitoring and error detection solutions. Among the many, the paper focuses on anomaly detection techniques, which monitor the evolution of some specific indicators through time to identify anomalies, i.e. deviations from the expected operational behavior. The timely identification of anomalies in dependable, fault tolerant systems allows to timely detect errors in the services and react appropriately. In this paper, we investigate the possibility to monitor the evolution of indicators through time using the random walk model on indicators belonging to Operating Systems, specifically in our study the Linux Red Hat EL5. The approach is based on the experimental evaluation of a large set of heterogeneous indicators, which are acquired under different operating conditions, both in terms of workload and faultload, on an air traffic management target system. The statistical analysis is based on a best-fitting approach aiming to minimize the integral distance between the empirical data distribution and some reference distributions. The outcomes of the analysis show that the idea of adopting a random walk model for the development of an anomaly detection monitor for critical systems that operates at Operating System level is promising. Moreover, standard distributions such as Laplace and Cauchy, rather than Normal, should be used for setting up the thresholds of the monitor. Further studies that involve a new application, a different Operating System and a new layer (an Application Server) will allow verifying the generalization of the approach to other fault tolerant systems, monitored layers and set of indicators.

An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

Reliable Hardware Architectures of the CORDIC Algorithm With a Fixed Angle of Rotations

Fixed-angle-rotation operation of vectors is widely used in signal processing, robotics, and graphics. Various optimized coordinate rotation digital computer (CORDIC) designs have been proposed for uniform rotation of vectors through known and specified angles. Nevertheless, in the presence of faults, such hardware architectures are potentially vulnerable. In this brief, we propose efficient error detection schemes for cascaded single-rotation CORDIC which hamper the performance of the architectures negligibly. We present signature-based schemes for this CORDIC variant to detect both transient and permanent faults. We further present how such schemes can be applied to other variants of CORDIC. The effectiveness of the proposed designs is assessed through field-programmable gate array implementations and error simulations. The results give confidence for the proposed efficient architectures which can be tailored based on the reliability requirements and overhead tolerance.

On Some Properties of the Mutual Information Between Extrinsics With Application to Iterative Decoding

Iterative decoding is an efficient error-correction tool based on the exchange of extrinsic probabilities between the constituent decoders. In this paper, the properties of the mutual information between the extrinsic LLR at the output of two constituent decoders are analyzed with application to turbo and LDPC codes. This is a bridge between information-theoretic analysis and practical implementations. It is proved here that the mutual information between extrinsics is a lower bound of the mutual information between each extrinsic and the transmitted message. In addition, an efficient online evaluation is provided in the paper with accuracy validated through numerical experiments. As an application, the mutual information between extrinsics is used for designing efficient stopping criterion and error detection rules at the decoder side. Two online methods for the estimation of optimal scaling factor to be applied to the extrinsic LLR are also derived. In contrast with most references, an analytical expression is obtained that does not require estimation of the actual transmitted bits. All results in the paper are derived for Gaussian distributed LLR with independent mean and variance.

Predicting errors from patterns of event-related potentials preceding an overt response

Everyday actions often require fast and efficient error detection and error correction. For this, the brain has to accumulate evidence for errors as soon as it becomes available. This study used multivariate pattern classification techniques for event-related potentials to track the accumulation of error-related brain activity before an overt response was made. Upcoming errors in a digit-flanker task could be predicted after the initiation of an erroneous motor response, ∼90ms before response execution. Channels over motor and parieto-occipital cortices were most important for error prediction, suggesting ongoing perceptual analyses and comparisons of initiated and appropriate motor programmes. Lower response force on error trials as compared to correct trials was observed, which indicates that this early error information was used for attempts to correct for errors before the overt response was made. In summary, our results suggest an early, automatic accumulation of error-related information, providing input for fast correction processes.

Fast, Simple, and Accurate: In Vivo Dosimeter Calibration for HDR/PDR Brachytherapy

In vivo dosimetry (IVD) during brachytherapy (BT) provides with an independent verification of the agreement between planned and delivered treatments. Despite several benefits from real-time IVD, e.g. efficient detection of treatment errors, widespread use of IVD is limited due to factors that compromise the simplicity of the implementation and the dosimetric accuracy. This study presents a fast and accurate calibration procedure for real-time point dosimeters which substantially simplifies clinical implementations of cost efficient and accurate IVD.

In vivo dosimetry: trends and prospects for brachytherapy.

The error types during brachytherapy (BT) treatments and their occurrence rates are not well known. The limited knowledge is partly attributed to the lack of independent verification systems of the treatment progression in the clinical workflow routine. Within the field of in vivo dosimetry (IVD), it is established that real-time IVD can provide efficient error detection and treatment verification. However, it is also recognized that widespread implementations are hampered by the lack of available high-accuracy IVD systems that are straightforward for the clinical staff to use. This article highlights the capabilities of the state-of-the-art IVD technology in the context of error detection and quality assurance (QA) and discusses related prospects of the latest developments within the field. The article emphasizes the main challenges responsible for the limited practice of IVD and provides descriptions on how they can be overcome. Finally, the article suggests a framework for collaborations between BT clinics that implemented IVD on a routine basis and postulates that such collaborations could improve BT QA measures and the knowledge about BT error types and their occurrence rates.