Efficient Circuit Simulation Research Articles

Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs

This paper presents a compact model for partially depleted SOI MOSFETs, which allows for describing the total dose and the single event effects. It incorporates both temperature and charge buildup effects during irradiation. The developed model is implemented in a Verilog-A module. This original module can be coupled with Spice simulator, allowing for faster (time efficient) circuit simulations (comparing to numerical physical ones) at different bias, linear energy transfer ( LET), buildup charges and temperatures. Better efficiency and flexibility than the standard current source method is achieved thanks to the direct link between the module and the irradiated transistor through the partially depleted SOI CMOS body contact terminal. Mixed-mode simulations of a partially depleted SOI CMOS D flip–flop at different conditions (biases, LETs, temperatures, buildup charge densities) are used in order to validate the model. Well-known high tolerance of SOI circuits to a single event effects is demonstrated to be degraded with the total dose increase (appearing as a positive charge buildup), which is further enhanced at higher temperatures.

SPICE Behavioral Model of the Tunneling Field-Effect Transistor for Circuit Simulation

The tunneling field-effect transistor (TFET) is an alternative device for deep-submicrometer CMOS with very good short channel and leakage characteristics. In this brief, a SPICE behavioral model that well captures the I- V characteristics and the parasitic capacitance of the n-channel TFET is proposed to facilitate efficient circuit design and simulation. The validity of the model is verified with technology computer-aided design (TCAD) simulation. The accuracy is within 10% and is of an order of magnitude faster than the TCAD.

A SPICE-Compatible New Silicon Nanowire Field-Effect Transistors (SNWFETs) Model

Extraction of carrier mobilities of silicon nanowire FETs (SNWFETs) with Schottky source and drain contacts is performed using a newly developed compact model, which is suitable for efficient circuit simulation. The SNWFET model is based on an equivalent circuit including a Schottky diode model for two metal-semiconductor contacts and a SPICE LEVEL 3 MOSFET model for an intrinsic NW. The Schottky diode model is based on our recently developed Schottky diode model that includes thermionic field emission for reverse bias and thermionic emission mechanism for forward bias. It also includes a new analytical Schottky barrier height model dependent on the gate voltages as well as the drain-source voltages. The results simulated from the SNWFET model reproduce various, previously reported experimental results within 10% errors. The mobilities extracted from our model are compared with the mobility calculated without considering the Schottky contacts.

The Mixed Time-Frequency Steady-State Analysis Method for Nonlinear Circuits Driven by Multitone Signals

This paper presents the mixed time-frequency steady-state analysis method for efficient simulation of circuits whose excitation frequencies are widely separated. These circuits can be written by multitime partial differential equations. In this paper, an axis of the slow time-scale is formulated in the time domain and another axis of the fast time-scale is formulated in the frequency domain. We show that computational cost, however, is not dependent on the interval of frequencies, whereas for the harmonic balance or transient analysis, it increases as the interval of frequencies increases.

Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO

Design optimization for performance enhancement in analog and mixed-signal circuits is an active area of research as technology scaling is moving towards the nanometer scale. This paper presents an approach towards the efficient simulation and characterization of mixed-signal circuits, using a 45nm CMOS voltage controlled oscillator (VCO) with frequency divider as a case study. The performance characteristics of the analog and digital blocks in the circuit are simulated and the accuracy issues arising due to separate analog and digital simulation engines are considered. The tremendous impact of gate tunneling current on device performance is quantitatively analyzed with the help of an “effective tunneling capacitance”, which allows accurate modeling and simulation of digital blocks with almost analog accuracy. To meet the design specifications of the analog VCO using digital CMOS technology, we follow a design of experiments (DOE) approach. The functional specifications of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate-oxide tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45nm and below. Due to the large number of available design parameter (gate-oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime.

Multirate models for simulating a colpitts oscillator

AbstractA model based on multirate partial differential algebraic equations yields an efficient numerical simulation of electric circuits in radio frequency applications. Considering frequency modulation, free parameters of the model are determined appropriately by a minimisation strategy. We apply the multirate approach to simulate a modified version of a Colpitts oscillator, which exhibits frequency modulation at widely separated time scales. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By one-step relaxation, only one Newton-Raphson iteration is performed for each faulty circuit with the dc solution of the good circuit as the initial point, and the approximate solution is used for detecting the fault. The paper shows experimentally and justifies theoretically that approximate dc fault simulation by one-step relaxation can accomplish almost the same fault coverage as exact dc fault simulation. Exact dc fault simulation by adaptive simulation continuation is first to order faulty circuits based on the results of one-step relaxation, and then to use the solution of the previous faulty circuit as the initial point for the Newton-Raphson iteration of the next faulty circuit. Experiments on a set of 29 MCNC Circuit Simulation and Modeling Workshop benchmark circuits show that exact dc fault simulation by adaptive simulation continuation can achieve an average speedup of 4.4 and as high as 15 over traditional stand-alone fault simulation

SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings

A new circuit analysis method, named SPICE-accurate iterative linear-centric analysis (SILCA), is proposed for the efficient and accurate time-domain simulation of deep submicron very large scale integrated (VLSI) circuits with strong parasitic couplings. SILCA consists of two key linear-centric techniques applied to time-domain nonlinear circuit simulation. For numerical integration, explicit-formula substitution and iterative-formula transformation are presented to convert implicit variable time-step integration to fixed leading coefficient (FLC) variable time-step integration. This paper characterizes both convergence and stability properties of the resulting FLC integration formulae. For nonlinear iteration, a successive variable chord (SVC) method is used as an alternative to the Newton-Raphson method. Further, the low-rank update technique is implemented for fast LU factorization. With these techniques, the number and cost of required LU factorizations are reduced dramatically. Experimental results on nonlinear circuits coupled with substrate and power/ground networks have demonstrated that SILCA achieves more than an order of magnitude speedup over SPICE3 in terms of both the cost of LU factorization and the overall CPU time. SILCA is suitable for efficient SPICE-like time-domain simulation of parasitic-coupled VLSI circuits, where the number of linear parasitic elements dominates the number of nonlinear devices

Application of the envelope-transient method to the analysis and design of autonomous circuits

The envelope transient enables a very efficient simulation of circuits with two different time scales, such as those that contain modulated signals (for example, amplifier or mixers), where an accurate prediction of intermodulation distortion is needed. The method has also been extended to oscillator analysis, where it requires additional techniques in order to avoid convergence to degenerate mathematical solutions, for which the circuit is not actually oscillating. It allows an efficient analysis of transients in these circuits and an accurate prediction of the phase-noise spectrum. This article presents an overview of the envelope-transient method and its most recent applications to the simulation of autonomous circuits, such as free and forced oscillators, frequency dividers, and phase-locked loops. Using this method, the operation bands of these circuits (which are delimited by qualitative stability changes or bifurcations) can be determined in a straightforward manner. This technique can also be applied to predict intermodulation distortion in self-oscillating mixers and to simulate the response of synchronized oscillators containing modulated signals. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2005.

Transient modelling of single-electron transistors for efficient circuit simulation by SPICE

In the paper, a regime, where the independent treatment of single-electron transistors (SETs) in transient simulations is valid, has been identified quantitatively. It is found that, as in the steady-state case, although the temperature varies, each SET can be treated independently, even in the transient case when the interconnection capacitance is large enough. However, the value of the load capacitance CL of the interconnections for the independent treatment of SETs is approximately ten times larger than that of the steady-state case. A compact SET transient model is developed for transient circuit simulation by SPICE. The developed model is based on a linearised equivalent circuit and the solution of a master equation is done by the programming capabilities of the SmartSpice. Exact delineation of several simulation time scales and the physics-based compact model make it possible to accurately simulate hybrid circuits in the timescales down to several tens of picoseconds.

A Coupled Efficient and Systematic Full-Wave Time-Domain Macromodeling and Circuit Simulation Method for Signal Integrity Analysis of High-Speed Interconnects

This paper presents an accurate and systematic approach for analysis of the signal integrity of the high-speed interconnects, which couples the full-wave finite difference time domain (FDTD) method with scattering (S) parameter based macromodeling by using rational function approximation and the circuit simulator. Firstly, the full-wave FDTD method is applied to characterize the interconnect subsystems, which is dedicated to extract the S parameters of the subnetwork consisting of interconnects with fairly complex geometry. Once the frequency-domain discrete data of the S parameters of the interconnect subnetwork is constructed, the rational function approximation is carried out to establish the macromodel of the interconnect subnetwork by employing the vector fitting method, which provides a more robust and accurate solution for the overall problem. Finally, the analysis of the signal integrity of the hybrid circuit can be fulfilled by using the S parameters based macromodel synthesis and simulation program with integrated circuits emphasis (SPICE) circuit simulator. Numerical experiments demonstrate that the proposed approach is accurate and efficient to address the hybrid electromagnetic (interconnect part) and circuit problems, in which the electromagnetic field effects are fully considered and the strength of SPICE circuit simulator is also exploited.

A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits

A multilayered integrated circuit (IC) package structure is composed of many signal layers, power layers, and ground layers. Particularly, the whole planes are assigned for the power and ground of the system. Accordingly, the generic circuit representation of such a complicated multilayer IC package becomes too complicated to efficiently evaluate its electrical performance. In this work, a novel compact package circuit model for the efficient simulation and analysis of such complicated IC packages is presented. Unlike the conventional models, current distributions within the package are modeled by introducing a compact partial plane circuit model. Thus, the proposed package model is much simpler than the conventional generic circuit models, while its accuracy is preserved. Thereby, today's complicated IC packages can be efficiently evaluated and analyzed. Its accuracy and efficiency are verified by benchmarking it with a conventional generic package circuit model; this conventional model may not be practical to use for package evaluation and analysis. It is then shown that the proposed model can be efficiently applied for the signal integrity verification of complicated IC packages and high-performance VLSI circuits.

Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model

This paper presents a simple, physics-based, and continuous model for the quantum effects and polydepletion in deep-submicrometer MOSFETs with very thin gate oxide thicknesses. This analytical design-oriented MOSFET model correctly predicts inversion and depletion charges, transcapacitances, and drain current, from weak to strong inversion and from nonsaturation to saturation. One single additional parameter is used for polysilicon doping concentration, while the quantum correction does not introduce any new parameter. Comparison to experimental data of deep-submicrometer technologies is provided, showing accurate fits both for I-V and C-V data. The model offers simple relationships among effective electrical parameters and physical device parameters, providing insight into the physical phenomena. This new model thereby supports device engineering, analog circuit design practice, as well as efficient circuit simulation.

Hazard Algebras

We introduce algebras capable of representing, detecting, identifying, and counting static and dynamic hazard pulses that can occur in the worst case on any wire in a gate circuit. These algebras also permit us to count the worst-case number of signal changes on any wire. This is of interest to logic designers for two reasons: each signal change consumes energy, and unnecessary multiple signal changes slow down the circuit operation. We describe efficient circuit simulation algorithms based on our algebras and illustrate them by several examples. Our method generalizes Eichelberger's ternary simulation and several other algebras designed for hazard detection.

Validity of mobility universality for scaled metal–oxide–semiconductor field-effect transistors down to 100 nm gate length

Mobility universality, confirmed for long-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), is demonstrated to be preserved for scaled MOSFET technologies down to 100 nm gate length, although phenomena such as quantum-mechanical and poly-silicon depletion effects play important roles. This result was obtained by applying a compact model based on the drift-diffusion approximation and relying only on Ids–Vgs measurements instead of using a conventional method with supplemental Cgate–Vgs measurements. It is confirmed that the carrier mobility is still governed by the electric field applied, and that the drift-diffusion approximation remains valid down to channel length of 100 nm. Consequently, the carrier behavior of such scaled small-size MOSFETs can be precisely described by simple analytical equations, which is important for the development of efficient circuit-simulation models.

Equivalent circuit approach for single electron transistor model for efficient circuit simulation by SPICE

A new compact DC/transient single electron transistor model for circuit simulation by SPICE is introduced. This model includes a newly developed equivalent circuit approach based on the time-dependent master equation and an exact conductance or transconductance model. The simulation speed of this model is improved, compared with that of the previous models.

A compact drain-current model for stacked-gate flash memory cells

In this paper, we present a compact single-piece and complete drain current model for submicron stacked-gate flash memory cells. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi-two-dimensional Poisson equation. The important short-channel device features: drain-capacitance coupling, drain-induced-barrier lowering, channel-length modulation, velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. This model is smoothly continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain currents with the experimental and the two-dimensional stimulated data.

Equivalent-circuit modeling and verification of metal-ceramic packages for RF and microwave power transistors

A modeling procedure was developed to generate electrical package models for metal-ceramic packages. These models are capable of accounting for package effects associated with the package lead capacitance, the self and mutual inductances of the bond wires, and the coupling between the input and output of the package. A combination of full-wave electromagnetic simulation and equivalent-circuit model extraction allows accurate model generation and efficient circuit simulation. Measured S-parameters were used to verify the overall modeling methodology. It has been demonstrated that the package effects play an important role in the accurate prediction of the packaged transistor performance.

Macromodeling of single-electron transistors for efficient circuit simulation

In this study, the possibility of compact modeling in single-electron circuit simulation has been investigated. It is found that each Coulomb island in single-electron circuits can be treated independently when the interconnections between single-electron transistors are large enough and a quantitative criterion for this condition is given. It is also demonstrated that, in those situations, SPICE macromodeling of single-electron transistors can be used for efficient circuit simulation. The developed macromodel produces simulation results with reasonable accuracy and with orders of magnitude less CPU time than usual Monte Carlo simulations.

Efficient circuit simulation of nonuniform transmission lines

This paper extends the transmission-line simulation method presented previously by Kuznetsov and Schutt-Aint (see IEEE Trans. Circuits Syst. I, vol. 43, p. 111-121, Feb. 1996) to nonuniform lines. The method is applicable to multiconductor lossy frequency-dependent transmission lines characterized by sampled frequency-domain responses. The resulting model can be directly incorporated into a circuit simulator. The implementation includes AC, DC, and transient analyses. The method is reliable, accurate, and as efficient as the simple replacement of interconnects by lumped resistors. The method is based on approximation, and its accuracy and efficiency result from the simplicity of characteristic responses. To apply the method to nonuniform lines, two novel nonuniform line models are introduced. An open-loop model completely separates forward and backward waves and results in the simplest aperiodic responses, but does not guarantee their stability. An open-loop distributed-reflection model explicitly includes the internal distributed reflections, and provides the simplest stable characterization. It is shown that for nonuniform lines, the generalized method of characteristics no longer separates forward and backward waves. Numerical example of a parabolically tapered frequency-dependent four-conductor line is given.