Effect Of Series Resistance Research Articles

Optimal Magnetic Field Shielding Method by Metallic Sheets in Wireless Power Transfer System

To meet the regulations established to limit human exposure to time-varying electromagnetic fields (EMFs) such as the International Committee on Non-Ionizing Radiation Protection (ICNIRP) guidelines, thin metallic sheets are often used to shield magnetic field leakage in high power applications of wireless power transfer (WPT) systems based on magnetic field coupling. However, the metals in the vicinity of the WPT coils cause the decrease of self and mutual inductances and increase of effective series resistance; as such, the electric performance including transmission power and the efficiency of the system is affected. With the research objective of further investigating excellent shielding effectiveness associated with system performance, the utilization of the optimal magnetic field shielding method by metallic sheets in magnetic field coupling WPT is carried out in this paper. The circuit and 3D Finite Element Analysis (FEA) models are combined to predict the magnetic field distribution and electrical performance. Simulation and experiment results show that the method is very effective by obtaining the largest possible coupling coefficient of the WPT coils within the allowable range and then reducing the value nearest to and no smaller than the critical coupling coefficient via geometric unbroken metallic sheets. The optimal magnetic field shielding method which considers the system efficiency, transmission power, transmission distance, and system size is also achieved using the analytic hierarchy process (AHP). The results can benefit WPT by helping to achieve efficient energy transfer and safe use in metal shielded equipment.

Illumination impact on electrical properties of Ag/0.6 wt% nanographene oxide doped poly(vinyl alcohol) nanocomposite/p-Si heterojunction

In present study, the electrical characteristics of the Ag/0.6 wt% nGO doped poly(vinyl alcohol) (PVA)/p-Si heterojunction were investigated using current–voltage (I–V) and capacitance-voltage (C-V) measurements under dark and white light (visible light) illuminations conditions at room temperature. The nanographene oxide (nGO) powders were prepared by using improved Hummers method. The structure and morphology of as obtained nGO-PVA/p-Si heterojunction were analyzed through SEM and EDX. The main parameters such as ideality factors (n), barrier heights (Φb0), series resistances (RS), and the density of interface states (NSS) have been investigated using current–voltage measurements under dark and illumination conditions at room temperature. The difference between the barrier heights obtained from the I–V and C–V characteristics has been discussed in dark and under illumination conditions. The barrier height, ideality factor and series resistance of the Ag/nGO-PVA/p-Si Schottky heterojunction have been also determined using Cheung's and Norde methods. In addition, the interface state density (NSS) as a function of energy distribution (ESS- EV) was extracted from the forward-bias I–V measurements by taking into account the bias dependence of the effective barrier height and series resistance. These results show that the 0.6% nGO-doped poly(vinyl alcohol) nanocomposite layer prevents reaction and inter-diffusion between Ag and p-Si as well as passivating the active dangling bonds at the semiconductor surface.

The competing roles of i-ZnO in Cu(In,Ga)Se2 solar cells

The electrical role of the highly resistive and transparent (HRT) i-ZnO layer in Cu(In, Ga)Se2(CIGS) solar cells is investigated. By tuning the resistivity of atomic layer deposited (ALD) i-ZnO through the use of post-growth O2-plasma treatments, it is shown that low i-ZnO carrier densities (i.e. high resistivities) actually restrict the performance of CIGS solar cells by reducing the extent of band-bending of the CdS/CIGS junction (the effect of series resistance is ruled out as the origin of any observed differences). This is the first evidence that i-ZnO has a negative electrical effect in CIGS solar cells (alongside the positive effect of shunt mitigation), and based on these results, attempts to maximise resistivity of the i-ZnO (typically sought-after for this HRT layer) are not recommended. Device efficiencies of 12.5% were obtained when using low resistivity as-grown ALD i-ZnO (resistivity, ρ=0.6Ωcm, carrier density, n=3.5·1018cm−3, and work function, Φ=4.06eV), but this decreased to 11.5% when using high resistivity, plasma-treated ALD i-ZnO (ρ=134Ωcm, n=0.2·1018cm−3, and Φ=4.21eV). SCAPS modelling revealed the reason for the difference to be the effect that the i-ZnO work function (controlled by carrier density) has on the band-bending and built-in voltage, Vbi, of the main junction. Capacitance-voltage experiments confirmed that the Vbi is lower (∆Vbi~0.1V) when using low carrier density, high resistivity i-ZnO. This general effect was also found when using RF-sputtered i-ZnO, whereby the inclusion of high resistivity i-ZnO similarly generated lower efficiencies (15.0%) than low resistivity i-ZnO (15.9%).

Temperature-Dependent Electrical Properties and Carrier Transport Mechanisms of TMAH-Treated Ni/Au/Al2O3/GaN MIS Diode

The temperature-dependent electrical properties and carrier transport mechanisms of tetramethylammonium hydroxide (TMAH)-treated Ni/Au/Al2O3/GaN metal–insulator–semiconductor (MIS) diodes have been investigated by current–voltage (I–V) and capacitance–voltage (C–V) measurements. The experimental results reveal that the barrier height (I–V) increases whereas the ideality factor decreases with increasing temperature. The TMAH-treated Ni/Au/Al2O3/GaN MIS diode showed nonideal behaviors which indicate the presence of a nonuniform distribution of interface states (NSS) and effect of series resistance (RS). The obtained RS and NSS were found to decrease with increasing temperature. Furthermore, it was found that different transport mechanisms dominated in the TMAH-treated Ni/Au/Al2O3/GaN MIS diode. At 150 K to 250 K, Poole–Frenkel emission (PFE) was found to be responsible for the reverse leakage, while Schottky emission (SE) was the dominant mechanism at high electric fields in the temperature range from 300 K to 400 K. Feasible energy band diagrams and possible carrier transport mechanisms for the TMAH-treated Ni/Au/Al2O3/GaN MIS diode are discussed based on PFE and SE.

A Dithering-Amplification-Based Identification Technique for Online SMPS

A novel nonparametric system identification (SI) algorithm is described, focusing on PID-based control loops for buck converters with effective series resistance (ESR) in the output filter. Dithering amplification effects on the control path are exploited during the steady-state converter operation. The noise injected is used to stimulate the loop reaction and to identify the output filter configuration. Oversampling-dithering features of third-order $\Delta \Sigma$ modulators are used to increase the DPWM resolution during the converter nominal operation and, moreover, as the core key to compute the SI algorithm. A modified structure of a noise shaper is used to handle the resolution of the SI algorithm over a range of the desired frequencies during the nonparametric identification. The SI algorithm comprises two steps: the first processing step extracts the resonant frequency, and the second extracts the ESR zero from the power spectrum density computation of the control feedback error. The SI method has been validated with different buck converter configurations, and has successfully been integrated and measured into a digitally controlled buck converters prototype for automotive safety application.

Influence of Silver-Aluminium Alloy at Solar Cell Rear Side on Series Resistance and Open Circuit Voltage

The rear side metallization of industrial PERC solar cells was investigated regarding the implication on the silver-aluminium-alloy formation, in particular the effect of the high resistivity alloy formation and the etching of surface passivation layer. By changing the dimensions of the printed silver-pads the size of the silver-aluminium-overlap region at the pad-aluminium interface were varied. The influence on fill factor and open circuit voltage are evaluated. For a three busbar cell design with six pads per busbar, the fill factor decreases up to 2.2%abs, if the overlap length between aluminium and silver pad is reduced from 12.5 mm to 1 mm, whereas the open circuit voltage increases by 2.5 mV. These results are additionally confirmed by a 3D simulation which validates the measurement results and shows perspectives for reducing the series resistance effect of the silver-aluminium overlap region up to 40% by increasing the busbar count from 3 to 5.

Structural and electrical characteristics of ALD-HfO2/n-Si gate stack with SiON interfacial layer for advanced CMOS technology

We report the fabrication of an ultra-thin silicon oxynitride (SiON) as an interfacial layer (IL) for n-Si/ALD-HfO2 gate stack with reduced leakage current. The XRD, AFM, FTIR, FESEM and EDAX characterizations have been performed for structural and morphological studies. Electrical parameters such as dielectric constant (K), interface trap density (Dit), leakage current density (J), effective oxide charge (Qeff), barrier height (Φbo), ideality factor (ƞ), breakdown-voltage (Vbr) and series resistance (Rs) were extracted through C-V, G-V and I-V measurements. The determined values of K, Dit, J, Qeff, Φbo, ƞ, Vbr and Rs are 14.4, 0.5 × 10 11 eV−1 cm−2, 2.2 × 10−9 A/cm2, 0.3 × 1013 cm−2, 0.42, 2.1, −0.33 and 14.5 MΩ respectively. SiON growth prior to HfO2 deposition has curtailed the problem of high leakage current density and interfacial traps due to sufficient amount of N2 incorporated at the interface.

Surface Nonuniformity-Induced Frequency Dispersion in Accumulation Capacitance for Silicon MOS(n) Capacitor

Frequency dispersion in accumulation capacitance is observed in Al/SiO2/n-Si structured MOS with an ultrathin oxide layer (2.8 nm) grown on roughened silicon surface. The measured accumulation capacitance shows a 14.9% (26.9%) decrease at 1-kHz measurement frequency, and a 50.3% (69.2%) decrease at 10-kHz measurement frequency for partially nonuniform (fully nonuniform) sample. This phenomenon can be attributed to the lateral series resistance in the surface accumulation layer due to the interaction between nonuniformly distributed electrons. By taking into account the effect of nonuniformity-induced lateral series resistance, the accumulation C-V can be reproduced from a simplified model with a carefully chosen effective series resistance Rs,eff. The extracted Rs,eff is found to be frequency dependent and the value increases with a larger percentage of the nonuniform area. On the other hand, for p-type MOS, inconspicuous frequency dispersion in accumulation capacitance but apparent distortion in C-V profiles is observed. The possible mechanisms for the phenomenon are discussed.

Series and parallel resistance effects on the C–V and G–V characteristics of $$\mathrm{Al}/\mathrm{SiO}_{2}$$ Al / SiO 2 /Si structure

This paper investigates the electrical behavior of the C---V and G---V characteristics of $$\mathrm{Al}/\mathrm{SiO}_{2}/\mathrm{Si}$$Al/SiO2/Si structure. The modeling of capacitance and conductance has been developed from complex admittance treatment applied to the proposed equivalent circuit. Poisson transport equations have been used to determine the charge density, surface potential, total capacitance, and flatband and threshold voltages as a function of the gate voltage, frequency ($$\omega )$$?), and series $$({R}_{\mathrm{s}})$$(Rs) and parallel $$({R}_{\mathrm{p}})$$(Rp) resistances. Results showed a frequency dispersion of C---V and G---V curves in both accumulation and inversion regimes. With increasing frequency, the accumulation capacitance is decreased, whereas the conductance is strongly increased. The shape, dispersion, and degradation of C---V and G---V characteristics are more influenced when parallel and series resistances $$(\mathrm{R}_{\mathrm{s}}$$(Rs, $$\mathrm{R}_{\mathrm{p}})$$Rp) are dependent to substrate doping density. The variation of $$\mathrm{R}_{\mathrm{s}}$$Rs and $$\mathrm{R}_{\mathrm{p}}$$Rp values led to a reduction of flatband voltage from ?1.40 to ?1.26 V and increase of the threshold voltage negatively from ?0.28 to ?0.74 V. A good agreement has been observed between simulated and measured C---V and G---V curves obtained at high frequency.

Effect of cryogenic temperature characteristics on 0.18-μm silicon-on-insulator devices**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176095 and 61404169) and the Youth Innovation Promotion Association of Chinese Academy of Sciences.

The experimental results of the cryogenic temperature characteristics on 0.18-μm silicon-on-insulator (SOI) metal-oxide-silicon (MOS) field-effect-transistors (FETs) were presented in detail. The current and capacitance characteristics for different operating conditions ranging from 300 K to 10 K were discussed. SOI MOSFETs at cryogenic temperature exhibit improved performance, as expected. Nevertheless, operation at cryogenic temperature also demonstrates abnormal behaviors, such as the impurity freeze-out and series resistance effects. In this paper, the critical parameters of the devices were extracted with a specific method from 300 K to 10 K. Accordingly, some temperature-dependent-parameter models were created to improve fitting precision at cryogenic temperature.

Modeling and Feedback Control of LLC Resonant Converters at High Switching Frequency

The high-switching-frequency operation of power converters can achieve high power density through size reduction of passive components, such as capacitors, inductors, and transformers. However, a small-output capacitor that has small capacitance and low effective series resistance changes the small-signal model of the converter power stage. Such a capacitor can make the converter unstable by increasing the crossover frequency in the transfer function of the small-signal model. In this paper, the design and implementation of a high-frequency LLC resonant converter are presented to verify the power density enhancement achieved by decreasing the size of passive components. The effect of small output capacitance is analyzed for stability by using a proper small-signal model of the LLC resonant converter. Finally, proper design methods of a feedback compensator are proposed to obtain a sufficient phase margin in the Bode plot of the loop gain of the converter for stable operation at 500 kHz switching frequency. A theoretical approach using MATLAB, a simulation approach using PSIM, and experimental results are presented to show the validity of the proposed analysis and design methods with 100 and 500 kHz prototype converters.

Series resistance effect on time zero dielectrics breakdown characteristics of MOSCAP with ultra-thin EOT high-k/metal gate stacks**Project supported by the National High Technology Research and Development Program (863 Program) of China (No. SS2015AA010601), the National Natural Science Foundation of China (Nos. 61176091, 61306129), and the Opening Project of the Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics,

The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler–Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process.

Description of the local series resistance of real solar cells by separate horizontal and vertical components

All previous concepts for describing the effective local series resistance of really existing solar cells, as it can be measured e.g. by luminescence imaging, try to describe it by a single local number. In solar cells showing an inhomogeneous saturation current density, this results in different series resistance images for the dark and illuminated case. The reason is the distributed character of the series resistance and the different diode current profiles under these different conditions. In this work the well-known finite element concept is used for describing a solar cell, which contains separate resistors carrying horizontal and vertical currents. A strategy is proposed how to fit these resistors to results of electroluminescence and lock-in thermography images of a real solar cell, leading to separate images of the local horizontal grid resistance, which may also show broken gridlines, and the local vertical׳lumped emitter contact resistance’. The latter lumps all resistive inhomogeneities of the cell, caused by a possibly inhomogeneous contact-, emitter-, grid-, bulk-, and back contact resistance. It will be shown that this description of the local series resistance reasonably describes both the dark and illuminated case, even in inhomogeneous multicrystalline silicon solar cells.

Silicon Nanowire Arrays for High Capacitance Electrodes in Room Temperature Ionic Liquid Electrolyte

Si has not been much considered as electrode material for capacitors due to a low specific capacitance and high reactivity with electrolytes, despite the benefits a μ-Si-based electrolytic capacitor can offer in integrated circuits. Recent investigations however, have shown that nanostructured Si electrodes with and without a protective coating demonstrate good capacitive ability [1]. In our work, we protect the Si nanowires (NWs) with a thin (<2nm) NAOS oxide (nitric acid oxidation) [2] and use a non-aqueous ionic liquid electrolyte, [Bmim][NTf2] in order to extend the operating voltage window of SiNW electrodes. In addition to the capacitor value, the effective series resistance is also important for efficient electrolytic capacitors. To reduce the electrode’s resistance, spin-on-doping (SOD) is used [2]. In this work, we investigate the influence of three different doping atoms: B, Ga and Al on the characteristics. All 3 are p-type doping in Si. The diffusion constant, D is DAl > DGa > DB. The starting wafer has a B doping of the order of ~5 1017 cm-3. Silicon Nanowire Arrays (SiNWAs) are fabricated by metal-assisted chemical etching (a solution-based process that produces Ag nanoparticles on the surface, forming the catalyst for local oxidation and etch of the Si), followed by SOD and anneal in an RTA (rapid thermal annealer); a buffered HF dip and NAOS at 120 °C for 10 min in 76% HNO3. Annealing of the SOD has been done in Ar for Ga and Al doping, but O2 for B to avoid the growth of a boron rich layer. The length of the NWs in the arrays is ~ 15 μm. Samples are characterised in a three-electrode setup by cyclic voltammetry (CV) at different scan rates (0.05 – 0.5 V/s) and electrical impedance spectroscopy (EIS). The results of the SOD samples were compared with a non-SOD sample. For large scan windows (2 – 2.5V) a redox reaction was observed for all samples except the Ga SOD sample. The redox peaks show very similar characteristics and are quasi-irreversibility. The B SOD sample has the smallest voltage window (~ 2V). The Ga doped sample did not show any redox reactions within a 3.5 V scan window. The maximum voltage window of [Bmim][NTf2] is 4V [2]. The maximum capacitance derived from the minimum currents in the CV with a large voltage window are: 0.3 mF·cm-2, 0.9 mF·cm-2, 1.0 mF·cm-2 and 2.3 mF·cm-2 for B, non-SOD, Al and Ga doped samples, respectively. These values are confirmed by the EIS measurements. The Ga doped SiNWA capacitance is found to be the best amongst those reported in literature. It remains to be investigated whether the introduction of Ga leads to an increase in corrosion resistance of the NWs. The resistance value derived from the EIS measurements is: 110 Ω, 60 Ω and 16 Ω for the B, Ga and Al SOD samples, respectively. The difference in resistance is in accordance with the diffusion constants of the doping atoms into Si. These resistance values however are still large and can be further reduced via multiple SOD implementations. Multiple SOD was tested for bulk Si with B which has shown a reduction of the resistance from 54 Ω in the 1st SOD step to 7 Ω in the 3rd step. Applying multiple SOD on the SiNWAs will decrease their resistance further. XPS might give an insight of the presence of any of the SOD related doping atoms on the SiO2 surface that might cause or limit redox reactions. The figures in the attachment show a cross section of a SiNWA, the CV for Ga doped SiNWAs for different scan rates and the extracted capacitance versus frequency plot from EIS measurements for the same electrode.

Effect of Post Plasma Oxidation on Ge Gate Stacks Interface Formation

One of the key challenges for Ge gate stack is to achieve an improved interface quality between Ge and the high-K dielectric. In order to overcome this limitation, various interface treatments like ozone pre-gate treatment and ozone ambient annealing (1), nitridation of Ge surface (2),formation of a GeO2 layer between Ge and high-K dielectric using ECR plasma technique (3) and formation of an ultra-thin SiO2/GeO2bilayer have been tried. It has recently been reported that slot plane antenna(SPA) microwave plasma treatment helps to improve the EOT and enhances the oxide quality by reducing impurities and leakage current when the dielectric is exposed during or after deposition (4). Moreover SPA oxidation possesses the unique property of having low electron temperature, which makes it a very low damage process compared to other techniques,either inductively coupled plasma(ICP) and electron cyclotron resonance(ECR) plasma (5). In this study we investigated the impact of SPA plasma oxidation (SPAO) treatment in improving the interface quality when MOS capacitors were fabricated on 300mm p-type Ge substrates. SPAO plasma treatments were performed at different steps in the high-k deposition process. The substrate was initially subjected to a dry chemical oxide removal (COR) process. Subsequently, three different sets of samples were prepared with the exposure of SPAO plasma at following locations (Fig.1): CASE-1: SPAO plasma treatment after Al2O3(1nm)/ZrO2(3.5nm) deposition; CASE-2: SPAO plasma treatment was carried out in between Al2O3(1nm) and ZrO2(3.5nm) deposition; CASE-3: the Ge substrate was exposed to SPAO plasma treatment after COR and prior to Al2O3(1nm)/ ZrO2(3.5nm) layer deposition. Al2O3(1nm) and ZrO2(3.5nm) layers were deposited by atomic layer deposition. Capacitance-voltage at multi-frequencies,current-voltage and conductance measurements were performed at room temperature. Parameters like flatband voltage (Vfb), equivalent oxide thickness(EOT), interface state density(Dit),and leakage current were estimated accurately after quantum mechanical corrections and eliminating the series resistance effect. As shown in Fig. 2 lowest fast interface state density is achieved when SPAO plasma treatment was performed after Al2O3 and prior to ZrO2 deposition (CASE-2). A comparable Dit is also observed when plasma exposure was done after the entire gate stack deposition (CASE-1) (Fig.2). From different experimental results significant degradation to both the dielectric quality and interface was observed when SPAO is performed just after COR (CASE-3).

Analysis of interface states of FeO-Al2O3 spinel composite film/p-Si diode by conductance technique

The interface states and series resistance properties of the Al/FeO-Al2O3/p-Si diode were investigated by the capacitance (C) and conductance (G) measurements. The measured capacitance and conductance values were corrected to eliminate the effect of series resistance to obtain the real capacitance and conductance values of the diode. The C and G characteristics indicate the presence of interface states at the interface of the diode. The interface states density, N ss, was determined using Hill–Coleman method, and it was found that the density of interface states is decreased with the frequency. The obtained results suggest that the series resistance and interface states affect significantly the electronic parameters of the Al/FeO-Al2O3/p-Si diode.

인덕터 내부저항을 고려한 LCL 필터의 능동댐핑 특성

LCL filters are widely used in high-order harmonics attenuation of output currents in grid-connected inverters. However, output currents of grid-connected inverters with LCL filters can become unstable because of the resonance of the filters. Given that the characteristics of output currents in inverters mostly depend on filter performance, the exact analysis of filters by considering parasitic components is necessary for both harmonics attenuation and current control. LCL filters have three or four parasitic components: the series and/or parallel resistance of the filter capacitor and the series resistance of the two filter inductors. Most studies on LCL filters have focused on the parasitic components of the filter capacitor. Although several studies have addressed the parasitic components of the filter inductor at the inverter side, no study has yet investigated the concurrent effects of series resistance in both filter inductors in detail. This paper analyzes LCL filters by considering series resistance in both filter inductors; it proposes an active damping method based on the virtual series resistance of LCL filters. The performance of the proposed active damping is then verified through both simulation and experiment using Hardware-in-the-Loop Simulator(HILS).

Study of self-compliance behaviors and internal filament characteristics in intrinsic SiOx-based resistive switching memory

Self-compliance characteristics and reliability optimization are investigated in intrinsic unipolar silicon oxide (SiOx)-based resistive switching (RS) memory using TiW/SiOx/TiW device structures. The program window (difference between SET voltage and RESET voltage) is dependent on external series resistance, demonstrating that the SET process is due to a voltage-triggered mechanism. The program window has been optimized for program/erase disturbance immunity and reliability for circuit-level applications. The SET and RESET transitions have also been characterized using a dynamic conductivity method, which distinguishes the self-compliance behavior due to an internal series resistance effect (filament) in SiOx-based RS memory. By using a conceptual “filament/resistive gap (GAP)” model of the conductive filament and a proton exchange model with appropriate assumptions, the internal filament resistance and GAP resistance can be estimated for high- and low-resistance states (HRS and LRS), and are found to be independent of external series resistance. Our experimental results not only provide insights into potential reliability issues but also help to clarify the switching mechanisms and device operating characteristics of SiOx-based RS memory.

The Effect of Interface States Density Distribution and Series Resistance on Electrical Behaviour of Schottky Diode

The forward and reverse bias current-voltage characteristics of the In/p-Si Schottky barrier diode (SBD) have been investigated in the temperature range of 360K to 120K. The current-voltage measurements have been used to extract the electrical parameters such as series resistance, barrier height, ideality factor and interface states density distribution. The higher values of series resistance, ideality factor and interface states energy distribution at low temperature was attributed to the presence of an interfacial insulated layer, popularly known as metal-insulator-semiconductor (MIS) devices. The temperature dependence energy distribution profile of interface states was obtained from the forward bias I-V-T measurements by taking into account the bias dependence of the effective barrier height and ideality factor. The interface states density (NSS) decreased with increasing temperature was explained by the result of atomic restructuring and reordering at the metal semiconductor interface.

Effect of environmental conditions on device and performance parameters of thin film photovoltaic modules

The effects of outdoor temperature and irradiance on the device and performance parameters of thin film amorphous hydrogenated silicon (a-Si:H) module are investigated. An outdoor test facility is installed to perform I-V measurements under different irradiance and temperature conditions. A numerical model considering the effect of series and shunt resistances is developed to determine different module parameters. The device parameters determined from I-V measurements are found to agree well with the corresponding parameters obtained from the developed model. The device parameters extracted from I-V measurements are then employed to investigate device parameters impacts on module performance parameters. Present results indicate that as outdoor temperature increases, the device parameters increase at all irradiance levels studied. Also, the device parameters decrease with increasing irradiance up to 800 W/m2 then the behaviour starts to be vice versa. While, Voc and Isc increase with irradiance but FF and η decrease.