Effects Of Parasitic Components Research Articles

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

K-band CMOS voltage-controlled oscillator using tail current modulation with half-output frequency

A CMOS voltage-controlled oscillator (VCO) using half-oscillation frequency signals as switched biasing is proposed to simultaneously improve the phase noise and DC-to-RF conversion efficiency. The effect of the flicker noise caused by the tail current source, which is the dominant factor of the VCO phase noise, can be reduced by the modulation using the half-frequency signals of the output. The conversion efficiency of the proposed VCO is improved by the leakage of the second harmonics of the modulation signal at the drain node of the current source, which is the same as the oscillation frequency of the VCO, thereby increasing the output power. The differential half-frequency signals are generated in the frequency divider, designed with the current-mode logic for minimizing the effect of parasitic components at high-frequency operation, which constitutes the frequency synthesizer without any additional circuits. The proposed VCO with the divider was fabricated on the size of 0.4 × 0.61 mm2 using a 65-nm CMOS process, including all pads. The measurement results showed a tuning range of 11.2% at the K-band and a phase noise of –109.86 dBc/Hz at the 1-MHz offset. The peak output power and DC-to-RF efficiency were measured to be 0.95 dBm and 16.64%, respectively, at the supply voltage of 1.2 V. A figure of merit of the proposed VCO was calculated to be –188.03 dBc/Hz.

Realization of a new PMOS transistors based first-order delay equalizer suitable for communication networks

In this paper, a novel first-order delay equalizer based on a PMOS transistor is proposed which is highly suitable for the communication systems and networks. The core circuit consists of three unity-gain PMOS inverting amplifiers, one resistor and one capacitor. The newly proposed delay equalizer has ability to provide both inverting all pass and non-inverting all pass responses simultaneously from the same structure without restriction of any matching of passive elements to achieve desired performance. High input and low output impedances enable cascadability in the proposed circuit. The circuit's behaviour under loading effects and the effect of parasitic components are also examined in detail. To assess the applicability of the proposed structure, nth-order delay equalizer is also presented. The performance of the proposed work is validated through PSPICE simulations utilizing TSMC 0.18 μm level-7 CMOS technology process parameters, with voltage levels set at ±0.9 V. Furthermore, real-time post-layout verification is being carried out to ensure the confirmed performance.

Design-Aware Parasitic-Aware Simulation Based Automation and Optimization of Highly Linear RF CMOS Power Amplifiers

In this paper, a parasitic-design-aware simulation-based design tool is proposed for highly linear RF power amplifiers. The main aim of the proposed tool is to speed up the design process of RF power amplifiers. In addition, it provides accurate final designs taking into consideration the effect of parasitic components of both active and passive devices. The proposed tool relies on the knowledge of designing highly linear RF power amplifiers. Both the optimization steps and design methodology are presented in this paper. The proposed tool is verified by designing a highly linear RF power amplifier at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node. The results show that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and OIP3 higher than 24 dBm at 6 dB back-off power can be obtained.

Parasitic Component Inclusive Optimum Phase-Frequency Contour Enabled Synchronous Rectification of Asymmetric CLLC Resonant Converter

With an objective to reduce the switching losses in a bidirectional resonant CLLC DC/DC converter for electric vehicle (EV) charging applications, this paper presents an elaborate frequency dependent general harmonic approximation (GHA) based secondary side turnoff current minimization technique by investigating the optimum operating point to achieve synchronous rectification (SR). Formulation of an accurate all-inclusive gain model is presented, specifically focusing on effect of parasitic components on the resultant gain-frequency trend, backed with thorough experimental validation. Further, meticulous modeling of the GHA based state equations is presented to obtain a contour of feasible operational frequencies and corresponding phase shifts to ascertain accurate SR operation with a multi-dimensional optimization technique to ensure reduced switching losses. In addition to that, to precisely characterize the resonant tank equivalent circuit, stressing on its effect on SR phase calculation, a detailed 3D finite element analysis (FEA) based R-L-C modelling of the employed high frequency planar transformer (HFPT) is explained. To validate and benchmark the performance of the proposed gain model while ensuring accurate SR operation, a 1kW all-GaN based CLLC experimental prototype is developed for a resonant frequency of 500kHz, with a power density of 106 W/inch <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . Experimental waveforms at corner conditions are presented for a wide-gain bidirectional operation, portraying a peak converter efficiency of 98.49%.

On-chip weak resistive defect diagnosis with performance enhancement in 45 nm technology static random access memory

Rapid advancement in deep submicron technology has resulted in the highest occupancy of memory on system-on-chip. The impact of process variations has increased with advanced technology in scaled devices. The reliability of the system majorly depends on embedded memory in the system. But the testing of recent Static Random Access Memory (SRAM) has become significantly difficult with advanced device scaling technology. The unavoidable flaws during fabrication and also the effect of process variations lead to resistive open defects in SRAM cells that change the cell behavior as well as impacts the capability of the fault detection scheme implemented on the system. The detection of weak resistive defects is becoming difficult in advanced technology memory devices. For reliable operation of the system, effective testing technology needs to be implemented for maximum coverage of defects in memory. This work proposes built-in circuitry integrated with SRAM to increase the resistive defect coverage and reduces separate testing circuit requirements. This paper evaluates the effectiveness of the proposed resistive defect detection technique, which uses a predischarged bit line with variable word line stress. Analysis of resistive defect detection by the proposed method is performed on a wide range of resistive open defects introduced at random locations in the memory, with the effects of parasitic components are also investigated for the detection of weak resistive defects. The proposed method implemented on 1 KB of memory provides a minimum area overhead of 3.87 % and the least penalty of 20.48 μs.

Distributed switched-resistor approach for high-Q biquad filters

The switched-resistor (S-R) approach is becoming more and more popular among integrated circuits designers because it allows the implementation of very high equivalent resistances in CMOS circuits. When using this technique, the value of a reference poly resistor is multiplied by a factor dependent on the duty cycle of the clock signal. To achieve resistance multiplication factors higher than 100, the value of the duty cycle has to be reduced below 0.01, but in this case the effects of parasitic components are not negligible anymore and the value of the equivalent resistance tends to saturate at a maximum value. In this paper, we present a distributed switched-resistor approach that aims to strongly mitigate the effect of parasitic capacitances on the value of the equivalent resistance even when exploiting very small values for the duty cycle, thus allowing resistance multiplication factors up to a few thousands. As a validation of this approach, we consider the implementation of a high Q biquad filter for neural recording applications and compare the conventional S-R technique against the proposed distributed S-R approach in terms of the maximum achievable Q factor.

Suppressing Voltage Spikes of MOSFET in H-Bridge Inverter Circuit

Power electronics devices are made from semiconductor switches such as thyristors, MOSFETs, and diodes, along with passive elements of inductors, capacitors, and resistors, and integrated circuits. They are heavily used in power processing for applications in computing, communication, medical electronics, appliance control, and as converters in high power DC and AC transmission in what is now called harmonized AC/DC networks. A converter’s operation is described as a periodic sequencing of different modes of operation corresponding to different topologies interfaced to filters made of passive elements. The performance of converters has improved considerably using high switching frequency, which leads to a significant improvement in a power converter’s performance. However, the high dv/dt through a fast-switching transient of the MOSFET is associated with parasitic components generating oscillations and voltage spikes having adverse effects on the operation of complementary switches, thereby affecting the safe operation of the power devices. In this paper, the MOSFET gate-driver circuit performance is improved to suppress the H-Bridge inverter’s voltage spikes. The proposed technique is a simple improvement to the gate driver based on the IR2112 driver (IC) by adding a capacitor to attenuate the effect of parasitic components and the freewheeling current, suppressing the negative voltage spikes. This paper’s main contribution is to improve the gate driver circuit’s capability for suppressing the voltage spikes in the H-Bridge inverter. The improved gate driver circuit is validated experimentally and is compared with the conventional gate driver. The experimental results show that the proposed technique can effectively suppress the MOSFET’s voltage spikes and oscillations.

A generalized common‐ground single‐switch continuous input‐current boost converter favourable for DC microgrids

SummaryThe conventional DC‑DC converters have limited voltage gain at moderate duty cycles. In theory, the large duty cycles should be adopted to reach large boosting factors. But in reality, at extreme duty cycles, the effect of parasitic components become dominant, which leads to increased voltage drops on devices, increased total loss and reduced efficiency. This paper proposes a single‐switch (requiring single gate‐driver circuit) diode‐inductor‐capacitor (DLC) cell‐based basic boost configuration that can solve the abovementioned issues. The employment of single‐switch has led to only two operational modes (in continuous conduction mode [CCM]) and easy control strategy. The continuous input‐current and large step‐up capability make the proposed configuration favourable for renewable or hybrid energy systems in DC microgrids. The simple configuration, modularity, moderate blocking voltage on semiconductors, wide duty‐cycle range, large voltage gains at low duty cycles, common‐ground between source and load are some profits of suggested configuration. The basic topology can be expanded by addition of DLC cells. Based on comparative analysis, the proposed configuration has larger step‐up capability per required components and lesser average normalized blocking voltage on semiconductors compared with other single‐switch topologies. This leads to smaller and cheaper structure with fewer losses. The configuration and operational modes of proposed basic topology (and its extended version) have been explained. Then, the design considerations and small‐signal modelling of basic topology have been investigated. Finally, the effectiveness and correct operation of proposed topology have been certified by comparative analysis and experimental results.

A Linear Current Driver for Efficient Illuminations and Visible Light Communications

This paper presents a linear current driver for simultaneous illuminations and high-speed visible light communications. Our proposed driver integrates a high-efficient converter, a preequalizer, and a high-bandwidth transconductor with an emitter equalizing stage together. In order to enhance the bandwidth and stability, we present an accurate model of our proposed driver to analyze the major impact factors precisely and to indicate the methods to eliminate the effects of parasitic components. Accordingly, we demonstrate a single-capacitor bypass compensation approach to improve the stability without reducing too much bandwidth. The experimental results are in good agreement with our theoretical model analyses and illustrate the optimal intervals for parameter configurations. Through the optimized implementation, we achieve a peak data rate of 2.0 Gb/s with 256-quadrature amplitude modulation (QAM), when driving ten series light-emitting diodes (LEDs) (12 W in total). The efficiency of transconductor core is 87%, and the overall efficiency is 76.6%. At the same time, the $-$ 6 dB bandwidth of this driver is expanded to 573 MHz in $-$ 20 dBS gain and 184 MHz in 0 dBS gain. The peak spectral efficiency enlargement compared to the conventional voltage driver is nearly 42.8% (from 128 to 1024 quadratic-amplitude modulation) under the same output power. To the best of our knowledge, this is the first report of implementing a high-power Gb/s visible light communication driver and efficient lighting simultaneously thus far.

공통모드 초크의 간단한 고주파 모델링 기법

In this paper, we analyze the effects of parasitic components of common-mode choke on the common mode and differential mode in a wide band, and we propose a simple method for high-frequency modeling. Common mode and differential mode 2-port networks were configured and the S-parameters in each mode were measured using a network analyzer. Equivalent circuit elements were extracted from the measured results to model a high-frequency equivalent circuit, and the validity was verified by comparing the measured S-parameters with the simulation results.

Sub-millimeter-Wave Equivalent Circuit Model for External Parasitics in Double-Finger HEMT Topologies

We present a novel distributed equivalent circuit that incorporates a three-way-coupled transmission line to accurately capture the external parasitics of double-finger high electron mobility transistor (HEMT) topologies up to 750 GHz. A six-step systematic parameter extraction procedure is used to determine the equivalent circuit elements for a representative device layout. The accuracy of the proposed approach is validated in the 90–750 GHz band through comparisons between measured data (via non-contact probing) and full-wave simulations, as well as the equivalent circuit response. Subsequently, a semi-distributed active device model is incorporated into the proposed parasitic circuit to demonstrate that the three-way-coupled transmission line model effectively predicts the adverse effect of parasitic components on the sub-mmW performance in an amplifier setting.

A Parasitic-Insensitive Charge Transfer Circuit for Capacitive Sensing using Active Output Voltage Feedback Technique

Abstract This paper introduces a new parasitic-insensitive charge transfer circuit using active output voltage feedback. The proposed parasitic-insensitive charge transfer circuit uses a passive charge transfer circuit for maximum output voltage dynamic range. A feedback loop between the transfer and output nodes is formed using a unity-gain opamp to make the two nodes’ potentials same, which prevents the charges stored at parasitic capacitors from transferring to the output. With those two characteristics, the proposed parasitic-insensitive charge transfer circuit offers full supply output voltage dynamic range for capacitive sensing without degradation of the linearity from the effects of parasitic components. The proposed parasitic-insensitive charge transfer circuit’s performances were simulated with standard 0.35μm CMOS technology and compared with those of a passive charge transfer circuit. It can be concluded from the results that the proposed parasitic-insensitive charge transfer circuit can be effectively used as a capacitive sensor with improved touch sensitivity for wider range of touch devices which include larger parasitic components.

Evaluation of Parasitic Components in LC Oscillators by Time-Varying Root-Locus

This paper presents an analysis of parasitic components associated with the physical design of low-noise LC oscillators utilizing time-varying root-locus (TVRL) method. The analysis demonstrates the effects of parasitic components on the LC oscillator operation, and in particular the effect on its phase noise performance. The precision of computing the roots with increased matrix sizes due to parasitic components is evaluated. The derived conclusions are verified by SpectreRF simulations on a previously reported VCO fabricated on 130 nm CMOS process.

Effects of Parasitic Components in High-FrequencyResonant Drivers for SynchronousRectification MOSFETs

Resonant drivers are usually employed for driving synchronous rectifier (SR) metal oxide semiconductor field effect transistors in high-frequency applications mainly because of their ability to supply high total gate charge in a very short time, while maintaining a high efficiency. However, their practical performance are strongly affected by parasitic components, whose effect is enhanced in applications requiring very high switching frequencies. In this paper, the effects of parasitic components in three different nonisolated resonant driver topologies are analyzed by considering their impact on the driver losses and on the SR gate voltage. The analyses and the experimental verifications reported in this paper originally show that, due to the internal parasitic inductance as well as the parasitic output capacitance of the driver switches, some driver topologies, in principle promising optimum performance, are not always the best solution for very high frequency applications. The more performing resonant driver, was also tested on the voltage regulator module working at 1.8 MHz reported in [21].

Power processor for interfacing battery storage system to 725V DC bus

The paper presents two high power, high frequency DC–DC power processors utilising a single phase AC link that is suitable for low voltage DC distribution systems. Expressions for active and apparent power transmitted through the isolation transformer and the primary side power factor are derived. The analysis accounts for the contribution made by harmonics towards power transmission. In the available literature, analysis of similar power processors ignores harmonics and assumes sinusoidal voltage and current waveform variation. It will be shown that ignoring power transfer due to harmonics leads to significantly lower calculated values of active and apparent power and to higher values of operating power factor compared with those obtained in practice. The best operating range of phase shift to ensure operation with high energy efficiency is identified. The effects of parasitic components on performance are also investigated. Simulation and analytical results for a 10 kW converter interconnecting 68–75/725 V DC busses are presented. Experimental results taken at a lower input voltage (24 V instead of 72) are also included to validate the simulation waveforms. 2006 Elsevier Ltd. All rights reserved.

The effect of parasitic components of GaAs FETs on high-frequency gain

Parasitic component effects on the gain of GaAs FETs are described. Numerical simulation shows that the frequency range of the unstable region (K < 1) of an FET decreases as gate resistance, drain resistance, or source inductance increases, and as source resistance decreases. The increase of gate or drain resistance does not affect MSG but does reduce MAG. The increase of source inductance or resistance reduces MSG and MAG. The Mag degradation is due to the decrease of |y21/y12| for the source resistance and the increase of K for the other parasitics. These findings should be helpful in the design and analysis of microwave GaAs FETS. © 1993 John Wiley & sons, Inc.