Evaluation of Parasitic Components in LC Oscillators by Time-Varying Root-Locus

Abstract

This paper presents an analysis of parasitic components associated with the physical design of low-noise LC oscillators utilizing time-varying root-locus (TVRL) method. The analysis demonstrates the effects of parasitic components on the LC oscillator operation, and in particular the effect on its phase noise performance. The precision of computing the roots with increased matrix sizes due to parasitic components is evaluated. The derived conclusions are verified by SpectreRF simulations on a previously reported VCO fabricated on 130 nm CMOS process.