Carrier Velocity Saturation Effects Research Articles

Robust Compact Model of High-Voltage MOSFET’s Drift Region

This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and behavioral issues that can arise in SPICE simulations with the existing current-dependent formulation in Berkeley-Short-Channel-IGFET model (BSIM) for HV transistors. We then demonstrate how a voltage-dependent formulation can mitigate them without losing simplicity and accuracy. We also validate the proposed model against experimental data of HV transistors.

Charge-Based Continuous Equations for the Transconductance and Output Conductance of Graded-Channel SOI MOSFET’s

This paper presents charge-based continuous equations for the transconductance and output conductance of submicrometer Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. The effects of carrier velocity saturation, channel length modulation and drain-induced barrier lowering were taken into account in the proposed equations. Experimental results were used to test the validity of the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement in a wide range of bias.

A novel approach for justification of box-triangular germanium profile in SiGe HBTs

This work presents a unique and robust approach for validation of using the box-triangular germanium profile in the base of SiGe heterojunction bipolar transistors, where the methodology considers the simultaneous optimization of the p-type base doping profile in conjunction with the germanium profile in the base. The study analyses the electron motion across the SiGe base in SiGe HBTs, owing to different accelerating electric fields. The analysis first presents a figure of merit, to achieve the minimum electron transit time across the base in conjunction with the increased current gain in n—p—n-SiGe HBTs, which shows a general trend vis-à-vis the advantage of a trapezoid germanium profile, but with additional accuracy as we considered simultaneously optimized p-type base doping. The effect of minority carrier velocity saturation is then included to make the study more detailed. The analysis then investigates the shifted germanium profile in the base to further minimize the base transit time. Finally, it is shown that a shifted germanium profile eventually evolves into a box-triangular Ge-profile in the SiGe base, which could simultaneously minimize the base transit time and reduce emitter delay by virtue of the high current gain. The analysis verifies that for an average Ge-dose of 7.5% Ge across the base, a box-triangular germanium profile in conjunction with an optimum base doping profile has an approximately identical base transit time and a 30% higher current gain, in comparison with an optimum base doping and triangular Ge-profile across the whole base.

Analytical modeling for drain current of strained Si NMOSFET

Based on the structure of strained Si/SiGe NMOSFET, a unified drain current model is presented in this paper. The model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a smoothing function, and guarantees the continuities of the drain current and its derivatives.Furthermore, the model accuracy is enhanced by including carrier velocity saturation and channel length modulation effects. Comparisons between the model and the measured data show that the drain current model can describe the device characteristics well. The proposed model is useful for the design and simulation of digital and analogy circuits made of strained Si.

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.

ANALYTICAL MODELING OF OVERSHOOTING EFFECT IN SUB-100 nm CMOS INVERTERS

Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations.

Empirical approach to the description of spectral performance degradation of silicon photodiodes used as particle detectors

The spectral deterioration of Hamamatsu S5821 silicon photodiodes for ion types and energies frequently used in Ion Beam Analysis was investigated. Focused proton beams with energies 430 keV and 2 MeV were applied to generate radiation damage via an area selective ion implantation in unbiased diodes at room temperature. The variations of spectroscopic features were measured “in situ” by Ion Beam Induced Current (IBIC) method as a function of fluence, within the 10 9–5 × 10 12 ion/cm 2 range and diode bias voltages, between 0 and 100 V. An empirical model has been developed to describe the radiation damage. Equations are derived for the variations of the normalized peak position and peak width. The derived empirical equations are physically correct, as far as they account for the superposition of the influence of charge carrier trapping by native and radiation-induced defects and for the effect of charge carrier velocity saturation with electric field strength, as well.

Specific features of dynamic injection and base layer modulation processes in power n +-p-p + diodes

The effect of electron-velocity saturation on the switch-on of an n{sup +}-p-p{sup +} structure in a quasi-neutral drift mode is considered. It is shown that electron-velocity saturation substantially decelerates the flight of the electron wave across the p-typebase of the n{sup +}-p-p{sup +} structure. This effect is also manifests itself in the stage of carrier accumulation in the p base of the structure. The velocity saturation effect is stronger, the thicker the base layer and the higher the rate at which the current flowing through the structure increases. The results obtained supplement the previously suggested classical description of the propagation of a minority carrier wave across the diode base layer, which disregards the effect of carrier velocity saturation. The results of an analytical calculation are confirmed by a numerical simulation.

Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation

One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage V dd , stable operation against V dd variations can be achieved with a simple circuit configuration. By using this, a 5 GHz amplifier has been designed and fabricated by using 0.18-μm CMOS process technology. The chip has been operated with a gain variation less than 1 dB having a peak gain of 13.5 dB from 1.2 to 2.9 V V dd .

Analytical model for base transit time of a bipolar transistor with Gaussian-doped base

The present analysis for base transit time τ b of a modern high-speed npn bipolar transistor is done for Gaussian-doped base considering doping dependence of mobility, bandgap narrowing effect and carrier velocity saturation effect at base–collector junction. First the minority carrier current density and electron density equations incorporating all the effects are analytically solved. The collector current density J c and base stored charge Q b are then separately expressed as a function of the injected electron density n(0) in the base in order to find base transit time. The modeling of J c, Q b and τ b are essential for the design of high-speed bipolar transistor. The equations are applicable for low level of injection. The base transit time calculated analytically is compared with numerical results in order to demonstrate the validity of the assumptions made in deriving the equations. The closed form equations for collector current density and base transit time offer a physical insight into device operation and are a useful tool in device design and optimization.

An Analytical Charge-Based Compact Delay Model for Submicrometer CMOS Inverters

We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the nth-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18-/spl mu/m and a 0.35-/spl mu/m process technologies show significant improvements over previous models.

Base transit time of graded-base Si/SiGe HBTs considering recombination lifetime and velocity saturation

The base transit time of Si/SiGe heterojunction bipolar transistor is analyzed including the effects of minority carrier recombination lifetime and velocity saturation. The reduction of recombination lifetime in the neutral base region increases the base transit time as compared to the infinite recombination lifetime, and the finite saturation velocity also degrades the base transit time, as compared to the infinite saturation velocity. This analytical analysis can obtain the optimum design of Ge profiles in the base to minimize the base transit time. The extremely heavy doping of the base can degrade the base transit time significantly if the base width is larger than the diffusion length.

Buffer delay change in the presence of power and ground noise

Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.

Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers

The authors present an accurate analytical method for analyzing the power consumption in CMOS buffers. It is derived from the charge transferred through the circuit and makes use of the physically based MM9 MOSFET model (Velghe et al., 1994), (Foty et al., 1997) as well as a modified Sakurai alpha-power law model. The resulting analytical model accounts for the effects of input slew time, device sizes, carrier velocity saturation effects, input-to-output coupling capacitance, output load, and temperature. Results are compared to HSPICE simulations (level 50) and to other models previously published considering a large set of parameters for a 0.18 and 0.35 /spl mu/m technologies, showing significant improvements.

Simultaneous switching noise analysis and low-bounce buffer design

An accurate equation to estimate simultaneous switching noise (SSN) created by CMOS output buffers is proposed. This analytic equation includes the carrier velocity saturation effects of a short-channel MOS transistor. Simulation results show that the proposed closed-form equation estimates the SSN precisely and the error is below 10% as compared with HSPICE simulation results. Design procedures of a low-bounce tapered buffer which take SSN into consideration are also proposed. Several output buffer design examples are demonstrated to show the significant improvement of the low-bounce buffer design. A test chip of the output buffer is implemented to operate at 400 MHz and the measurement results match the design specifications.

Compact LDD nMOSFET degradation model

In this paper, we present a compact degraded I-V model for submicron lightly-doped drain (LDD) MOSFET's. The analytical and physics-based model was developed using the drift equation and considering the nonuniform spatial hot-carrier-induced interface states and the detailed LDD structure. It can be used to calculate fresh channel electric field and drain current by turning off the effect of hot-carrier-induced interface states. Using the fresh electric field in conjunction with a simplified energy balance equation, the nonuniform spatial distribution of induced interface states ran be calculated. By incorporating this distribution into the degraded current model, we can describe the damaged I-V characteristics and channel electric fields as a function of stress time. The model includes the effects of series resistances and carrier velocity saturation. It can be used to calculate time-dependent degraded drain current, and is a time-saving CAD model.

Power and delay macro-modeling for submicronic CMOS process: Application to low power design

Designing in the deep submicronic range implies to manage trade off between speed and power. This paper presents an improved macro model for the delay and power dissipation of CMOS structures. This model is based on a simple but realistic MOS model to include the carrier velocity saturation effect of submicronic MOSFET's, the input-to-output coupling capacitance and the short circuit effects. These effects are responsible of the non-linear relationship between the inverter real delay and the input ramp rise or fall time. A complete representation is obtained in analytical equations of the delay and the power dissipation which give performance values in excellent agreement if compared to simulated ones (SPICE level 6). This has been validated on a .65 micron process, using the complete foundry specification for a large extent of input slope configurations ( τ IN t HLS = 1–20 ) and inverter internal configuration ratios. Applications are given to temperature effects in low voltage designs, low power buffer design and to standard cell performance characterization.

Electromagnetic investigation on the propagation in distributed active devices

An electromagnetic model for the study of the propagation mechanisms in distributed FET components, including conductor and dielectric losses, is proposed. The model also describes the effect of carrier-velocity saturation and finite carrier-transit time. Amplification is treated under the small-signal assumption. The method is applied to the characterisation of a GW-TWFET and a set of basic considerations and some design guidelines are provided which derive from an analysis of the energy constraints.

A high-power millimeter-wave frequency doubler using a planar diode array

A balanced frequency doubler has been built using an integrated planar array of four varactor diodes. The maximum output power of 55 mW at 174 GHz is twice the power available from the previous best multiplier at a nearby frequency and was limited by the available pump source. The peak efficiency is 25% at 150 mW input. Circuit parasitics and device heating do not appear to be significant at the present power levels and carrier velocity saturation effects appear to be reduced due to the series array configuration. >

Effects of carrier-velocity saturation on the characteristics of short channel MOSFETs with lightly doped drains

physica status solidi (a)Volume 131, Issue 1 p. K77-K80 Short Note Effects of carrier-velocity saturation on the characteristics of short channel MOSFETs with lightly doped drains M. B. Lee, M. B. Lee Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorJ. I. Lee, J. I. Lee Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorK. N. Kang, K. N. Kang Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorK. S. Yoon, K. S. Yoon Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Information Engineering Department, Korea University, Jochiwon, Chungnam 339–800, KoreaSearch for more papers by this authorS. Hong, S. Hong Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Electrical Engineering Department, Korea Advanced Institute ofence and Technology, 400, Kusong-Dong, Youson-Ku, Taejon 305–701, KoreaSearch for more papers by this authorK. Y. Lim, K. Y. Lim Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Physics Department, Jeonbuk National University, Jeonjoo, Jeonbuk 560–756, KoreaSearch for more papers by this author M. B. Lee, M. B. Lee Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorJ. I. Lee, J. I. Lee Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorK. N. Kang, K. N. Kang Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorK. S. Yoon, K. S. Yoon Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Information Engineering Department, Korea University, Jochiwon, Chungnam 339–800, KoreaSearch for more papers by this authorS. Hong, S. Hong Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Electrical Engineering Department, Korea Advanced Institute ofence and Technology, 400, Kusong-Dong, Youson-Ku, Taejon 305–701, KoreaSearch for more papers by this authorK. Y. Lim, K. Y. Lim Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Physics Department, Jeonbuk National University, Jeonjoo, Jeonbuk 560–756, KoreaSearch for more papers by this author First published: 16 May 1992 https://doi.org/10.1002/pssa.2211310149Citations: 1 Cheongryang, P.O. Box 131, Seoul 130–650, Korea. AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat Citing Literature Volume131, Issue116 May 1992Pages K77-K80 RelatedInformation