Power and delay macro-modeling for submicronic CMOS process: Application to low power design

Abstract

Designing in the deep submicronic range implies to manage trade off between speed and power. This paper presents an improved macro model for the delay and power dissipation of CMOS structures. This model is based on a simple but realistic MOS model to include the carrier velocity saturation effect of submicronic MOSFET's, the input-to-output coupling capacitance and the short circuit effects. These effects are responsible of the non-linear relationship between the inverter real delay and the input ramp rise or fall time. A complete representation is obtained in analytical equations of the delay and the power dissipation which give performance values in excellent agreement if compared to simulated ones (SPICE level 6). This has been validated on a .65 micron process, using the complete foundry specification for a large extent of input slope configurations ( τ IN t HLS = 1–20 ) and inverter internal configuration ratios. Applications are given to temperature effects in low voltage designs, low power buffer design and to standard cell performance characterization.