Effective Stress Time Research Articles

Scalar- and vector-valued seismic fragility assessment of segmental shield tunnel lining in liquefiable soil deposits

Seismic fragility analysis can quantitatively evaluate the seismic performance of structures from a probabilistic viewpoint and accurately characterize the relationship between the degree of structural damage and ground motion intensity. This study investigates the seismic fragility of shield tunnels in three different liquefiable and non-liquefiable soils. A plane-strain finite element model of the saturated soil and shield tunnel is established via the OpenSees computational platform employing the multi-yield surface elastoplastic PressureDependMultiYield and PressureIndependMultiYield models to simulate the constitutive behaviour of liquefiable and non-liquefiable soils. The developed model is utilized to conduct nonlinear dynamic effective stress time history analyses to generate the seismic fragility curves and surfaces based on the incremental dynamic analysis method. Meanwhile, appropriate scalar- and vector-valued intensity measures are identified based on their correlation, efficiency, practicality and proficiency. Compared with the fragility curves based on scalar-valued intensity measures, the fragility surfaces based on the vector-valued intensity measures can better describe the effect of ground motion characteristics on the structural seismic demand, and thus can more accurately assess the structural seismic performance. The seismic damage probabilities derived from the fragility curves and surfaces reveal that the seismic damage risk of the shield tunnel in sandwiched liquefiable soil deposit is higher than that of the tunnel structure located in entirely liquefiable or non-liquefiable soil profiles. This finding underscores the importance of carefully evaluating the seismic safety of shield tunnels situated in sandwiched liquefiable soil deposits.

Physical insight into the abnormal VTH instability of Schottky p-GaN HEMTs under high-frequency operation

In this Letter, we investigate the threshold voltage (VTH) instability of Schottky p-GaN gate high electron mobility transistors (SP-HEMTs) under high-frequency operation by a resistive-load hard switching method. The abnormal VTH instability is observed, which is different between fully and partially depleted SP-HEMTs (FD- and PD-HEMTs). Notably, for FD-HEMT, VTH shifts positively with effective stress time. However, the VTH instability in PD-HEMT is more complex. At low VGS (e.g., 3 V) and high VGS (e.g., 6 V), VTH shifts positively with stress time consistently. Nevertheless, at intermediate VGS levels (e.g., 4 and 5 V), VTH initially shifts positively and then negatively, displaying a non-monotonous variation. Furthermore, the frequency dependence of VTH is contingent upon VGS. At low VGS, VTH exhibits a negative shift with the increase in frequency. This trend inverses when VGS exceeds 4 V. And it should be noted that the extracted VTH under high-frequency operation is lower than their quasi-static values for both transistor types. This work depicts the physical process and mechanism of the abnormal VTH instability; different from the quasi-static case, hole accumulation effects will be enhanced due to the high dV/dt, which results in a lower VTH. The distinct VTH behaviors of FD- and PD-HEMTs are closely related to the trapping effects, as well as hole accumulation and insufficiency, within the two different p-GaN gate layers.

3D Effective stress analyses of dynamic LNG tank performance on liquefiable soils improved with stone columns

The seismic performance of an LNG tank on liquefiable soil improved with stone columns is assessed through 3D effective stress time history analyses. The numerical methodology, which is validated against centrifuge tests, uses the Ta-Ger model to capture the complex sand response under earthquake loading while it simultaneously accounts for Soil-Foundation-Structure interaction by incorporating tank inertial response and both convective and impulsive hydrodynamic actions through a system of properly calibrated oscillators. The methodology introduces a novel technique for incorporating the "improvement" effect of the stone columns by means of "equivalent" soil properties calibrated through separate analyses of a representative remediated 3D soil "cell" explicitly simulating the stone columns within the soil. The analyses show that the presence of the stone columns substantially reduces shear deformations in the improved soil. During shaking, tank settlements accumulate through a rocking, downwards ratcheting, mechanism, which is however constrained by the formation of a stable, nonliquefied soil zone below the tank. Post-seismic, reconsolidation settlements, primarily originating from unimproved zones below the stone columns, are also assessed. Once the complex soil behavior- and dynamic load- mechanisms are comprehensively addressed, differential settlements remain well below allowable limits, demonstrating adequate structure performance even under the high design shaking levels.

Alternately Controlled Optical Pixel Sensor System Using Amorphous Silicon Thin-Film Transistors

This paper presents an optical pixel sensor system that uses hydrogenated amorphous silicon (a-Si:H) photo thin-film transistors (TFTs) for innovating the user interface of displays with optical input functions. The proposed optical pixel sensor applies photo TFTs that are combined with one primary color filter (red, green, or blue) to determine the input signal to the optical sensor. Other photo TFTs covered with filters of other colors are utilized to provide compensating photocurrents for achieving a robust optical input function with a high signal-to-noise ratio under intense ambient white light. To improve the lifetime of the sensor and the degradation of photo TFTs under constant drain-to-source voltage (VDS) bias stress, an alternately controlled sensing structure is proposed to reduce the effective stress time of the photo TFTs. The optical characteristics and the degradation of a-Si:H photo TFTs under VDS stress with different duty ratios are investigated to verify the effect of reduced stress time on photo TFTs. Measurements further reveal that the proposed optical sensor achieves a significant initial difference in output voltages under high-intensity ambient white light of 13 230 lx, and that the difference remains high after 408 h of long-term operation at 70 °C, demonstrating the feasibility of the alternately controlled sensing structure and the long-term reliability of the sensor.

Pulse duration effect during pulsed gate-bias stress in a-InGaZnO thin film transistors

We investigated how the zero-voltage duration (0Vd) affects the tendency of degradation during pulsed gate bias stress in a-InGaZnO thin film transistors (TFTs). DC or pulsed negative bias illumination stress (NBIS) or positive bias stress (PBS) was applied to the TFTs for effective stress time of 4,000 s. While pulsed bias stress was being applied, stress-voltage duration (SVd) was set as either 10 s or 1 s per cycle, and 0Vd was varied from 100% to 1% of the SVd. During NBIS, degradation in both threshold voltage and sub-threshold slope became increasingly severe as 0Vd was shortened. However, during pulsed PBS, these trends were almost absent. These different tendencies may occur because the cause of each stress-induced degradation is fundamentally dissimilar; NBIS involves ionization of oxygen vacancies, whereas PBS involves electron trapping. The proposed mechanism was supported by additional bias stress tests on TFTs that had been immersed in H2O, where hydrogen became dominant factor causing the degradation.

Evaluation of effective stress times and stress levels from mission profiles for semiconductor reliability

Lifetime and duty cycles of automotive electronics are increasing, inducing new challenges to reliability predictions and testing. For qualification purposes, the automotive industry generates various time-dependent mission profiles with various stressors and varying stress levels according to different use cases.We present a theoretical model, describing the common approach, to reduce the stressors from time-dependent mission profiles to the two single parameters “effective stress level” and “effective stress time” for equivalent reliability testing. In a first step, the cumulative exposure (CE) model is shown to describe the future reliability behaviour after steplike stress level changes. Taking into account the individual characteristic lifetimes T63 of the corresponding Weibull distributions, in a second step, an effective T63 lifetime can be derived. For this calculation, periodic stress cycles are defined and transformed into an equivalent effective stress level. This procedure confirms the industry-wide used approach of dealing with effective stress levels for reliability testing.For the experimental validation metal-oxide-semiconductor (MOS) capacitors are fabricated and stressed by voltage and temperature. The received reliability data fit the theoretical predictions within the statistical variations.

Local-Degradation-Induced Threshold Voltage Shift in Turned-OFF Amorphous InGaZnO Thin Film Transistors Under AC Drain Bias Stress

Local degradation caused by drain bias ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {\mathbf {DS}}}$ </tex-math></inline-formula> ) stressing is recently considered as a key issue in amorphous InGaZnO (a-IGZO) thin film transistors (TFTs). In this letter, we investigate the instability of turned-OFF a-IGZO TFTs under ac <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {\mathbf {DS}}}$ </tex-math></inline-formula> stressing. The negative threshold voltage shift, which was well fitted by a stretched exponential function, was accelerated with increasing duty cycle despite the same effective stress time. A capacitance measurement reveals that a higher duty cycle induced more donor states near the drain, implying that the stretched-exponential time dependence cannot be fully explained by trapping mechanism. Temperature-dependent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau $ </tex-math></inline-formula> followed the Arrhenius relation, whereas <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> showed unusual temperature dependence in contrast to that under dc <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {\mathbf {DS}}}$ </tex-math></inline-formula> stressing. These findings suggest an additional origin such as a stress release effect under an ac <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {\mathbf {DS}}}$ </tex-math></inline-formula> stress other than hopping/tunneling mechanism.

Effect of Rising Edge in Dynamic Stress with Various Duty Ratio in Amorphous Ingazno Thin Film Transistor

Recently, many research explains the positive threshold voltage (V th ) shift of oxide TFT as charge trapping at gate dielectric or interface of gate dielectric and channel layer. But mechanism of degradation of rising edge of dynamic stress has not been explained exactly. During all stresses, gate stress of 1 Hz with 50%, 20%, 10% and 1% duty ratio was applied at 120 ℃ and both drain voltage and source voltage were grounded. Gate voltage (VG ) was on-voltage (Von ) of 20 V and off-voltage (Voff ) of 0 V in unipolar positive stress, Von of 0 V and Voff of -20 V in unipolar negative stress, and Von of 20 V and Voff of -20 V in bipolar stress (Fig.1). During illumination, samples were illuminated using a top LED. We defined Vth as gate voltage at 1 nA of drain current ID at VDS of 15V. We defined effective time as sum of Von time in all stress including illumination Fig. 2 shows the ΔVth as function of time with 50%, 20% 10% and 1% duty ratio. In dark, positive unipolar gate stress was applied in fig. 2(a) and bipolar gate stress was applied in fig. 2(b). In illumination, positive unipolar gate stress was applied in fig. 2(c) and bipolar gate stress was applied in fig. 2(d). Fig. 3 shows the ΔVth at effective time of 2000s as reciprocal function of duty ratio for positive unipolar gate stress and bipolar gate stress. At same effective stress time, ΔVth was increase with decreasing duty ratio and ΔVth was larger in bipolar gate stress than in unipolar positive gate stress. Fig. 4 shows ΔVth at effective time of 2000s as reciprocal function of duty ratio under positive unipolar gate stress for illumination and dark. In dark, higher ΔVth was observed compared with illumination. In this study, we investigated relationship of ΔVth with various bias stress condition including positive unipolar, negative unipolar and bipolar gate stress and ambient including dark and illumination. We will explain positive bias temperature stress based on charge trapping and introduce new mechanism of additional positive ΔVth on rising edge of dynamic stress. Figure 1

The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications

The dependence of bias temperature instability (BTI) and hot carrier injection (HCI)-induced frequency degradation on interconnect length has been examined for the first time. Experimental data from 65-nm test chips show that frequency degradation due to BTI decreases monotonically for longer wires because of the shorter effective stress time, while the HCI-induced component has a nonmonotonic relationship with interconnect length due to the combined effect of increased effective stress time and decreased effective stress voltage. Simple aging models are proposed to capture the unique BTI and HCI behavior in global interconnect drivers. A closed-loop simulation methodology that takes into consideration the interplay between the frequency degradation and the stress parameters (such as stress duration and stress voltage) is used to determine the optimal repeater count and sizing in practical interconnect circuits.

Experimental study of micro electrical discharge machining discharges

Micro electrical discharge machining (μEDM) is an atmospheric-pressure plasma-assisted technology that uses point-to-plane discharges in liquid dielectrics to remove microscopic quantities of electrically conductive materials. In this work, an innovative μEDM prototype machine was specifically designed and fabricated to produce and control single spark discharges, thus, resolving the typical limitations of (multi-discharge) commercial machines. The work analyses the type of discharge and the micro-plasma electron-density values obtained for 0.5–38 μm gap sizes, 3–10 000 μs pulse durations, 75–250 V low breakdown voltages, and 1–20 A discharge currents, using different combinations of metallic electrodes in oil and in water. Results allow fitting, for micro-scale and low voltages, an empirical law between the maximum gap-size for breakdown, the breakdown voltage, and the effective stress-time. The electron density ne is obtained by optical emission spectroscopy diagnostics of the Hα-line Stark broadening (yielding ne∼1016−1017 cm−3, i.e., ionization degrees of ∼2×10−5−10−4) and by a semi-empirical resistive plasma model. The model uses the experimental values of several electrical and geometrical quantities, and of the gas pressure estimated as ∼60 bar−2 kbar from measurements of the plasma mechanical action, obtained using a force sensor. The quantitative information of this phenomenological study can assist the optimization of this micro-fabrication technique.

P-y Plasticity Model for Nonlinear Dynamic Analysis of Piles in Liquefiable Soil

Liquefiable soil-structure interaction material models are developed and implemented in the open-source finite-element modeling platform OpenSees. Inputs to the free end of the p-y materials include the ground motion and mean effective stress time series from a free-field soil column. Example simulations using a single p-y element attached to a soil element demonstrate key features. The models are then used to analyze centrifuge experiments of a single pile in a level liquefiable profile and a six-pile group in a sloping liquefiable profile that resulted in lateral spreading. Measured displacements and mean effective stress time series are used as inputs to isolate the response of the material models from predictive uncertainties in free-field ground motion and excess pore pressure. The predicted pile response agrees reasonably well with measurements. The cyclic mobility behavior of sand in undrained loading is shown to be an important mechanism affecting bending moments in the piles; neglecting the dilatancy component of the sand's response (i.e., ignoring the cyclic mobility behavior) can result in underprediction of the demands imposed on the piles.

Investigating Degradation Behavior of InGaZnO Thin-Film Transistors Induced by Charge-Trapping Effect under DC and AC Gate-Bias Stress

This paper investigates the degradation mechanism of amorphous InGaZnO thin-film transistors under DC and AC gate bias stress. Comparing the degradation behavior at equal accumulated effective stress time, more pronounced threshold voltage shift under AC positive gate bias stress in comparison with DC stress indicates extra electron-trapping phenomenon occurs during the duration of rising/falling time in pulse. Contrarily, illuminated AC negative gate bias stress exhibits much less threshold voltage shift than DC stress, which suggesting the photo-generated hole does not has sufficient time to drift to the interface of IGZO/gate insulator and causes hole-trapping under AC operation. Since the evolution of threshold voltage fits the stretched-exponential equation well, the different degradation tendencies under DC/AC stress can be attributed to the different electron- and hole-trapping efficiencies, and this is further verified by varying pulse waveform.

Highly stable amorphous indium–gallium–zinc-oxide thin-film transistor using an etch-stopper and a via-hole structure

Highly stable amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etch-stopper and via-hole structure. The TFTs exhibited 40 cm2/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (Δ V th) at room temperature. The excellent stability is attributed to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at 60°C showed that there was a smaller Δ V th in the AC stress compared with the DC stress for the same effective stress time, indicating that the trapping of the carriers at the active layer–gate insulator interface was the dominant degradation mechanism.

Accurate negative bias temperature instability lifetime prediction based on hole injection

Negative bias temperature instability (NBTI) lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration is described and lifetime comparison between SiO 2 film and SiON film is made based on the prediction method. The acceleration parameters are most important for the accurate lifetime prediction. The proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but quantity of the hole injection to the gate insulator film that directly relates with the quantity of holes in the inversion layer. The degradation mechanism under the excessive voltage and excessive temperature stresses are different from that in the operation conditions. Using the hole injection method, the NBTI lifetime of SiON is less than that of SiO 2. This result agrees with the reported results measured by conventional high gate fields and temperatures. By the introduction of effective stress time (= Q hole/ J inj0), accurate lifetime prediction in terms of the V th shift is realized, and by analyzing of relationship between I D reduction and V th shift, accurate lifetime prediction in terms of the I D reduction and the degradation prediction in the circuit level are realized. These results are essential for the accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm.

Hot-carrier degradation analysis based on ring oscillators

This paper presents a new test circuit for hot-carrier degradation analysis based on a ring oscillator. The devices and the test circuit were fabricated using Philips’ 0.35 μm CMOS technology. For single device, AC and DC hot-carrier-induced degradation are the same if the effective stress time is carefully taken into account. For circuit level degradation, the frequency of the ring oscillator, on logarithmic scale degrades at the same slope as the saturation drain current of nMOS transistor degrades, while pMOS transistor degradation is much smaller than nMOSFET degradation and can be ignored. For universal applications, the circuit degradation can be expressed by MOSFETs I dsat degradation with NSF (nMOSFET degradation speed factor) and PSF (pMOSFET degradation speed factor). Formulae for NSF and PSF calculations are derived. Simulations with Philips PSTAR circuit simulator were also performed, which well agree with the experiment results.

Hot-carrier effects in scaled MOS devices

A universal guideline and state-of-the-art hot-carrier effects in scaled MOSFETs are reviewed and discussed from the viewpoints of 1) DC and AC hot-carrier effects, 2) hot-carrier detrapping phenomena, 3) mechanical stress effects on hot-carrier phenomena, and 4) hot-carrier resistant device structures. In the deep-submicron region, the hot-carrier applicable voltage is less than 3 V, so AC hot-carrier effects from the dynamic operation of actual circuits should be taken into account. Despite much experimentation and analysis, there is still no universally accepted theory that explain the AC degradation mechanism. This is because the noise caused by the wiring inductance in ULSI circuits and in measurement systems screens the intrinsic AC hot-carrier effects. Here, AC hot-carrier degradation enhanced by gate pulse-induced-noise is analyzed experimentally and theoretically. After eliminating the noise problem, it is found that AC hot-carrier degradation in LDD (Lightly doped drain) and GOLD (gate-drain overlapped device) structures can be estimated based on DC degradation in terms of the effective stress time which takes the duty ratio into account. In addition, it is found that the noise is negligible when the wiring inductance is smaller that 80 nH (250 mω), which is important for future circuit design. Furthermore, hot-carrier detrapping effects, especially in p-channel MOS devices, and hot-carrier phenomena under mechanical stress are investigated experimentally to better understand the underlying hot-carrier physics. Finally, future hot-carrier resistant device structures are discussed.