Effects Of Reactive Ion Etching Research Articles

Effect of Reactive Ion Etching on the Luminescence of GeV Color Centers in CVD Diamond Nanocrystals.

The negatively charged germanium-vacancy GeV− color centers in diamond nanocrystals are solid-state photon emitters suited for quantum information technologies, bio-sensing, and labeling applications. Due to the small Huang–Rhys factor, the GeV−-center zero-phonon line emission is expected to be very intensive and spectrally narrow. However, structural defects and the inhomogeneous distribution of local strains in the nanodiamonds result in the essential broadening of the ZPL. Therefore, clarification and elimination of the reasons for the broadening of the GeV− center ZPL is an important problem. We report on the effect of reactive ion etching in oxygen plasma on the structure and luminescence properties of nanodiamonds grown by hot filament chemical vapor deposition. Emission of GeV− color centers ensembles at about 602 nm in as-grown and etched nanodiamonds is probed using micro-photoluminescence and micro-Raman spectroscopy at room and liquid nitrogen temperature. We show that the etching removes the nanodiamond surface sp2-induced defects resulting in a reduction in the broad luminescence background and a narrowing of the diamond Raman band. The zero-phonon luminescence band of the ensemble of the GeV− centers is a superposition of narrow lines originated most likely from the GeV− center sub-ensembles under different uniaxial local strain conditions.

Isotropic Oxidation by Plasma Oxidation and Investigation of RIE Induced Effects for Development of 4H-SiC Trench MOSFETs

In this work, we examined the oxidation growth rates of the (0001) Si-face and (11−20) a-faces of 4H-SiC by carrying out oxidation in the 850°C-950 °C temperature range in a plasma afterglow furnace for application to trench MOSFETs. At 900 °C, this method results in almost equal oxide thickness on the Si-face and a-face which would nominally correspond to trench bottom and sidewalls in trench devices. Our results indicate that after NO annealing, the electronic properties of the plasma oxidized SiO2/SiC interface is comparable to control samples with gate oxides formed by dry oxidation at 1150 °C followed by NO annealing. Next, the effect of reactive ion etching (RIE) of 4H-SiC surfaces prior to gate oxidation was investigated using planar 4H-SiC MOS capacitors. Our experiments show that oxidation followed by NO annealing of surfaces with smooth morphology following the RIE step, results in similar interface charge and trap densities as MOS capacitors which did not undergo the RIE etching.

Deposition and Patterning of Polycrystalline Diamond Films Using Traditional Photolithography and Reactive Ion Etching

Given the exceptional characteristics of diamond films, they have become increasingly popular in the fields of medicine, microelectronics, and detector electronics. However, despite all the advantages, there are many technological problems that complicate their widespread application and impose limitations on diamond use in technological processes. In this study, we proposed a new technique for obtaining a complex topology of polycrystalline diamond coatings by selective seeding of the substrate by nucleation centers and subsequent surface treatment with reactive ion etching to reduce the number of parasitic particles. As a result, diamond films were obtained with a high particle concentration in the film region and high repeatability of the pattern. Moreover, parasitic particles influenced neutralization in areas where film coverage was not needed. The effect of the diamond nanoparticle concentration in a photoresist and the effect of reactive ion etching on the formation of a continuous film and the removal of parasitic nucleation centers were examined. The relative simplicity, low power consumption, and high efficiency of this method make it attractive for both industrial and scientific applications.

The effect of reactive ion etch (RIE) process conditions on ReRAM device performance

The recent surge of research on resistive random access memory (ReRAM) devices has resulted in a wealth of different materials and fabrication approaches. In this work, we describe the performance implications of utilizing a reactive ion etch (RIE) based process to fabricate HfO2 based ReRAM devices, versus a more unconventional shadow mask fabrication approach. The work is the result of an effort to increase device yield and reduce individual device size. Our results show that choice of RIE etch gas (SF6 versus CF4) is critical for defining the post-etch device profile (cross-section), and for tuning the removal of metal layers used as bottom electrodes in the ReRAM device stack. We have shown that etch conditions leading to a tapered profile for the device stack cause poor electrical performance, likely due to metal re-deposition during etching, and damage to the switching layer. These devices exhibit nonlinear I–V during the low resistive state, but this could be improved to linear behavior once a near-vertical etch profile was achieved. Device stacks with vertical etch profiles also showed an increase in forming voltage, reduced switching variability and increased endurance.

Effect of Reactive Ion Etch on 4H-SiC Mos Capacitor Performances

4H- Silicon carbide is a promising for power electronic devices operated at high voltages, high temperatures, and high frequencies due to its attractive material properties, such as high avalanche electric breakdown field (2.5 MV/cm), high electron mobility (1000 cm2/V. s), high thermal conductivity (4.9 Wcm-1K-1) and large bandgap (3.26 eV). While conventional double-implanted MOSFET (D-MOSFET) has been commercially successful, trench MOSFET is a fascinating device design for next-generation 4H-SiC power MOSFETs due to its low specific on resistance (RON) [1] and higher current density which can potentially reduce cost. Trench formation in mechanically hard and chemically stable 4H-SiC material requires reactive ion etching (RIE). This RIE step has been reported to introduce surface roughness and deep level defects [2-4] in SiC which may cause degradation of the channel mobility as well as the voltage blocking capability of the trench MOSFETs. These particular issues are critical challenges and need further attention. In this regard, we have studied the electrical properties of planer MOS capacitors fabricated on Si-face (<0001>) and A- face (<11–20>) 4H-SiC epitaxial layers, with and without RIE, prior to gate oxidation. Capacitance coupled plasma (CCP) RIE process was carried out to etch about 2μm of SiC, using NF3as the process gas. Before performing the gate oxidation, a sacrificial thermal oxidation was carried out on the etched samples to consume subsurface damage. The gate oxidation was followed annealing in nitric oxide (NO) for both etched and un-etched samples. Atomic force microscope (AFM) images revealed that almost atomically flat surfaces (RMS roughness= 0.3 nm) were obtained following RIEs as shows in Figure 1. Simultaneous high-low capacitance-voltage (C-V) measurements at room temperature was carried out to investigate RIE induced effects on effective charge density at the SiO2/4H-SiC interface and the interface trap density (Dit ) near the conduction band-edge of 4H-SiC. In addition, current-voltage (I-V) measurements were done at room temperature to investigate RIE induced dielectric breakdown effects. From the room temperature C-V data as shown in the Figure 2, it can be seen that C-V curves for MOS capacitors with or without RIE lie on top each with negligible flat-band voltage (VFB ) shift which suggests that the effective interfacial charge does not change significantly due to RIE (Table 1). Furthermore, extracted Dit profiles (Figure 3) with or without RIE MOS capacitors also shows no difference. In addition, comparable I-V data as shown in the Figure 4 also confirmed minimal effects induced by RIE. These results are inconsistent with previous results [4] where RIE was shown to generate significant amount of interface traps. This is most likely due to a much smoother surface obtained here after RIE as well the post-RIE sacrificial oxidation step which was implemented here. These results suggest that processes such as etching in an H2 environment at elevated temperatures not be necessary after RIE for trench MOSFET fabrication. In the ongoing work, we are analyzing possible deep level defects in the SiC bulk, introduced by RIE using deep level transient spectroscopy measurements. In this talk, detailed discussion of the methods in the context of trench MOSFETs and analysis of the obtained results will present. [1] B. J. Baliga, Fundamentals of power semiconductor devices 2010 (Springer Science & Business Media) [2] V. Khemka et al.: J. Electron. Mater. 27 (1998) 1128-1135 [3] K. Kawahara et al.: J. Appl. Phys. 108 (2010) 023706 [4] Gang Liu et al.: Appl. Surf. Sci. 324 (2015) 30–34 Figure 1

Controlling silicon crystallization in aluminum-induced crystallization via substrate plasma treatment

The effect of reactive ion etching using chlorine or fluorine-based plasmas on aluminum-induced crystallization (AIC) of silicon on fused silica glass substrates was investigated with the goal of chemically modifying the substrate surface and thereby influencing the crystallization behavior. Chlorine etching of the glass prior to AIC resulted in six times faster silicon crystallization times and smaller grain sizes than films formed on untreated substrates while fluorine etching resulted in crystallization times double than those on untreated surfaces. The differences in crystallization behavior were attributed to changes in surface chemistry and surface energy of the glass as a result of the plasma treatment as supported by X-ray photoelectron spectroscopy and contact angle measurements. The different surface treatments were then combined with optical lithography to control the location of crystallization on the substrate surface to realize the production of patterned polycrystalline silicon films from initially continuous aluminum and silicon.

Effect of Reactive Ion Etch on the Polishing Selectivity during Silicon Nitride Chemical Mechanical Polishing for Sub-10 nm Logic Device

Silicon nitride (SiN) Chemical Mechanical Polishing (CMP) was adopted to create a metal gate capped with dielectric material (SiN) for self-aligned contact (SAC) processing in replacement metal gate (RMG) procedures for the development of sub-10 nm logic devices. Based on the sub-10 nm device integration scheme, SiN CMP removes SiN film and stops on an oxide layer. Therefore it requires high selectivity between SiN and oxide film. The SiN CMP slurries developed for this purpose, show more than 30:1 SiN removal selectivity to oxide from the blanket wafers. However, the selectivity from the pattern wafers is less than 3:1. This study investigates the selectivity difference between blanket wafer and pattern wafer. For pattern wafers, the process flow includes reactive ion etching to recess tungsten metal gates. During this process, the oxide properties are changed. X-ray Photoelectron Spectroscopy (XPS) was used to analyze the film property after reactive ion etching. Depending on etch conditions, polishing removal selectivity is sensitively influenced. The etch process effect on CMP selectivity was investigated in this study.

Effect of reactive ion etching on the surface of polymethylmethacrylate

The influence of oxygen-, fluorine-, and argon-containing plasmas on the morphology of the surface of polymethylmethacrylate during reactive ion etching is investigated. A series of experiments on polymer surface etching microns is performed at different gas compositions (O2, N2, Ar, O2/N2, O2/Ar, CF4, and O2/CF4). It is demonstrated that the etching depth and surface roughness of the material increase with increasing RF oscillator power and, moreover, depend considerably on the composition and percentage ratio of gases injected into the chamber.

Surface Roughness Influence on O&lt;sub&gt;2 &lt;/sub&gt;and Ar RIE Gas Treated Aluminum Surface

This study reports on the preliminary investigations on the effect of Reactive Ion Etch (RIE) parameters on the surface characteristics of Al bond pad. Investigation is done employing Design of Experiment (DOE) method. Quantity of Oxygen, Argon, ICP power and BIAS power were varied to get 16 sets of recipes. This provides 16 samples with different combination of RIE parameters. Surface characteristics of the samples were analyzed using Atomic Force Microscopy (AFM).Data collected were in terms of Surface Roughness (RA), Peak Vs Valley (P-V) and Surface Root-Mean-Square Roughness (RMS). Result shows that combination of these RIE parameters does not vastly affect the surface characteristics of the Al bond pad.

Reactive Ion Etching Parameter Effect on Aluminum Bond Pad Surface Morphology

Reactive Ion Etching (RIE) is an important process in fabrication of semiconductor devices. Design Of Experiment (DOE) has been used to study the effect of Reactive Ion Etch (RIE) towards surface morphology of aluminum bond pad. Important RIE factors involved in this experimental study are ratio of Tetrafluoromethane (CF4), Argon gas flow, BIAS, and ICP power. Different combinations of these factors produces different results of surface morphologies which was obtained using Atomic Force Microscopic (AFM). Produced results shows that overall surface roughness of the pad is affected by RIE and DOE offers a better way to optimize the desired outcome.

Wettability and Surface Roughness Study on RIE Treated Aluminium Deposited Surface

Design of Experiment (DOE) is a technique for optimizing process which has controllable inputs and measurable outputs. As a method of DOE, 24 Full Factorial design is used to study the effect of Reactive Ion Etch towards the surface roughness of aluminum pad and effect of the roughness produced towards the contact angle. Surface roughness analysis is done using Atomic Force Microscop (AFM). Contact angle is measured using AutoCad software from the images captured from droplet test. This contact angles must be more than 90° for non-wetting profile or less than 90° for wetting profile. This work is also done to understand the interaction between the process parameters and how each parameters will affect the etch rate. The results are analyzed which shows that the increase in surface roughness produces an increase on the contact angle and vice versa.

Reactive Ion Etching Parameter Effect on Aluminum Bond Pad Surface Morphology

Reactive Ion Etching (RIE) is an important process in fabrication of semiconductor devices. Design Of Experiment (DOE) has been used to study the effect of Reactive Ion Etch (RIE) towards surface morphology of aluminum bond pad. Important RIE factors involved in this experimental study are ratio of Tetrafluoromethane (CF4), Argon gas flow, BIAS, and ICP power. Different combinations of these factors produces different results of surface morphologies which was obtained using Atomic Force Microscopic (AFM). Produced results shows that overall surface roughness of the pad is affected by RIE and DOE offers a better way to optimize the desired outcome.

Highly reliable passivation layer for a-InGaZnO thin-film transistors fabricated using polysilsesquioxane

ABSTRACTPolysilsesquioxane passivation layers were used to passivate bottom gate a-InGaZnO (a-IGZO) thin film transistors (TFT). The a-IGZO TFTs passivated with polysilsesquioxane showed highly stable behavior during positive bias stress, negative bias stress, and negative bias illumination stress. A voltage threshold shift of up to 0.1 V, less than -0.1 V and -2.3 V for positive bias stress, negative bias stress, and negative bias illumination stress, respectively. We also report the effect of reactive ion etching (RIE) on the electrical characteristics of a-InGaZnO (a-IGZO) thin-film transistors (TFT) passivated with the polysilsesquioxane-based passivation layers. We show how post-annealing treatment using two different atmosphere conditions: under O2 ambient and combination of N2 and O2 ambient (20% O2), can be performed to recover the initial characteristics. Furthermore, we present a highly stable novel polysilsesquioxane photosensitive passivation material that can be used to completely circumvent the reactive ion etching effects.

Aluminium Surface Grain Size Analysis on RIE Treatment

Reactive Ion Etch (RIE) has been an important process in the world of microelectronic fabrication. Focus of this preliminary study is on how RIE affects the grain size of aluminum film which is fabricated on substrates. RIE parameters are varied to obtain 16 different recipes which are done using Design of Experiment. Grain size of the samples is recorded for all 16 samples before and after RIE treatment. This produces results that can be compared to obtain the effect of RIE on the aluminum film. Results show that RIE affects the mean grain size of the aluminum film as it increases after RIE treatment.

Improvement of polycrystalline silicon wafer solar cell efficiency by forming nanoscale pyramids on wafer surface using a self-mask etching technique

The creation of nanostructures on polycrystalline silicon wafer surface to reduce the solar reflection can enhance the solar absorption and thus increase the solar-electricity conversion efficiency of solar cells. The self-masking reactive ion etching (RIE) was studied to directly fabricate nanostructures on silicon surface without using a masking process for antireflection purpose. Reactive gases comprising chlorine (Cl2), sulfur hexafluoride (SF6), and oxygen (O2) were activated by radio-frequency plasma in an RIE system at a typical pressure of 120-130 mTorr to fabricate the nanoscale pyramids. Poly-Si wafers were etched directly without masking for 6-10 min to create surface nanostructures by varying the compositions of SF6, Cl2, and O2 gas mixtures in the etching process. The wafers were then treated with acid (KOH:H2O = 1:1) for 1 min to remove the damage layer (100 nm) induced by dry etching. The damage layer significantly reduced the solar cell efficiencies by affecting the electrical properties of the surface layer. The light reflectivity from the surface after acid treatment could be significantly reduced to <10% for the wavelengths between 500 and 900 nm. The effects of RIE and surface treatment conditions on the surface nanostructures and the optical performance as well as the efficiencies of solar cells will be presented and discussed. The authors have successfully fabricated large-area (156 × 156 mm2) subwavelength antireflection structure on poly-Si substrates, which could improve the solar cell efficiency reproducibly up to 16.27%, higher than 15.56% using wet etching.

Accurate Reactive Ion Etching of Si, Ge and P Doped Ge in an SF6-O2 Radio-Frequency Plasma

The effect of reactive ion etching (RIE) of Silicon (Si), Germanium (Ge) and highly phosphorous doped Germanium (Ge:P) in an SF6-O2 plasma has been studied. We find that the etch characteristics of etch rate and sidewall profile are greatly affected by the O2 content. Etching rates of Ge and Ge:P depend on the O2 content with a significant reduction up to 20% of O2. We also find that an anisotropic sidewall etching mechanism exists and is dependent on the percentage of O2 (%O2) in the plasma. Sidewall angles range from a minimum of 66° to a maximum of 166°, where a critical concentration for etching angle exists where the etching angle can alternate from below 90° to above 90°. In combination, both features allow for precision plasma etching of Si, Ge and Ge:P.

Deep-level trapping centers in heterostructures for GaN field-effect transistors

Structural and electrophysical properties of heteroepitaxial gallium nitride layers on a sapphire substrate that are grown via the molecular beam epitaxy (MBE) method are studied. The parameters of deep-level trapping centers are determined by the method of the thermostimulated capacitor discharge; the degree of perfection of the film and substrate are determined by the two-crystal X-ray spectrometry method. The following structures are studied: i-GaN (1–2 µm)/GaN 〈Si〉(0.1−0.4 µm) and multilayer structures (Al0.3Ga0.7N-GaN-Al0.3-Ga0.7N-GaN-Al2O3) grown via the MBE method on a sapphire substrate. The effect of reactive ion etching on the energy spectrum of deep-level trapping centers in gallium nitride is studied. The obtained results are used to calculate the energy spectrum of defects in gallium nitride structures.

Effect of Reactive-Ion Etching on Thermal Oxide Properties on 4H-SiC

4H-SiC MOS capacitors were used to characterize the effect of reactive-ion etching of the SiC surface on the electrical properties of N2O-grown thermal oxides. The oxide breakdown field reduces from 9.5 MV/cm with wet etching to saturate at 9.0 MV/cm with 30% reactive-ion over-etching. Additionally, the conduction-band offset barrier height, φB, progressively decreases from 2.51 eV with wet etching to 2.46 eV with 45% reactive-ion over-etching.

RIE EFFECT ON THE FERROELECTRIC PROPERTIES

ABSTRACT Reactive Ion Etching (RIE) is used to etch the ferroelectric layer for the ferroelectric random access memories (FeRAMs) research, and the effect of RIE on the ferroelectric properties has been studied. The top platinum layer is etched by Ion Beam Etching (IBE) method, little polarization change has been observed after top electrode etching. The ferroelectric layer is etched by RIE, positive ions bombing the sample during etching and result in the positive ions left in the films. A significant polarization suppression has been found for the capacitors because of large amount ions existed in the films. The polarization can be recovered well after RTP annealing. However, the polarization decreases rapidly during fatigue test, which indicats that the introduced ions have not been removed completely after RTP annealing. On the contrary, the capacitor exhibits better fatigue behaviour because of few ions remained in the film after furnace annealing.

The effect of fluorine-based plasma treatment on morphology and chemical surface composition of biocompatible silicone elastomer

X-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM) have been used to investigate the effect of reactive ion etching (RIE) on poly(methylhydrogensiloxane-co-dimethylsiloxane) surface in fluorine-based plasmas. Polysiloxane layers supported on the standard silicon wafers were etched using SF 6 + O 2 or CF 4 + O 2 plasmas. SEM studies show that the polysiloxane morphology depends on plasma chemical composition strongly. Presence of a columnar layer likely covered with a fluorine rich compound was found on the elastomer surface after the CF 4 + O 2 plasma exposure. After the SF 6 + O 2 or CF 4 + O 2 plasma treatment the polysiloxane surface enriches with fluorine or with fluorine and aluminum, respectively. Different morphologies and surface chemical compositions of the silicone elastomer etched in both plasmas indicate different etching mechanisms.