Effect Of Parasitic Inductance Research Articles

Universal Synchronous Rectification Scheme for LLC Resonant Converter Using Primary-Side Inductor Voltage

In recent years, many advanced modulation strategies have been applied in LLC resonant converters, resulting in the increased demand for the synchronous rectification (SR) schemes without modulation strategy limitation. However, the conventional universal SR schemes are mainly on the basis of primary/secondary side current or drain-source voltage of synchronous rectifiers, which are limited by high cost of current transformer (CT) and loss of duty cycle caused by parasitic inductance, respectively. To deal with these problems, this paper proposes a novel SR scheme for LLC resonant converter. Firstly, a SR analysis method on the basis of the idea of power transmission is proposed. It can decouple SR from modulation strategy. Based on this method, this paper proposes a universal SR scheme using primary-side inductor voltage. The scheme is no longer restricted by the modulation strategy of converter. Meanwhile, no CT is required, thereby reducing the cost and conduction loss. Thanks to the large signal sensing-based, this scheme has good noise immunity. Moreover, it eliminates the negative effect of parasitic inductance by integral operation. With these effects, it has high accuracy of SR. Furthermore, an easily-debugged analog implementation is designed, which only needs to adjust one component parameter. Finally, experimental results show that the proposed scheme is compatible with different modulation strategies, and it has higher efficiency than the commercial SR scheme in a wide range of operating conditions.

Causes and Solutions for the Mal-operation of Differential Pressure Protection of Substation

The capacitor compensation circuit of the traction substation is affected by high-harmonics and the differential voltage protection is frequently mal-operation, which causes serious disturbance to the railroad transportation order. In this paper, the effect of parasitic inductance of capacitor banks and the parameter characteristics under high harmonics are analyzed by establishing the high-frequency circuit structure of capacitor banks. Then, a fitting formula describing the differential voltage is established based on the measured data to describe the frequency variation characteristics of the differential voltage value. Finally, a solution to the problem of differential voltage protection mal-operation of capacitor banks is discussed, a Resistance-Capacitance filter circuit is designed, and the effectiveness is verified by simulation.

A DC Solid-State Circuit Breaker Based on Transient Current Commutation

This article proposes a new dc solid-state circuit breaker (SSCB) based on silicon carbide (SiC) MOSFETs. There are two main contributions. First, a transient current commutation (TCC) is obtained in the main switch during current interruption. To achieve this, a compact and fast active injection circuit (AIC) is employed. TCC brings two main benefits: 1) it eliminates the effects of parasitic inductances in circuit connections and removes voltage oscillations on the gate of the main switch, which prevents spurious turn-on and 2) it eliminates the transient power shock on the switch during turn-off, which extends the lifetime of SSCB and increases its reliability. Second, the voltage on the employed metal oxide varistor (MOV) is reduced to zero during the OFF-state. This extends the maximum allowable dc bus voltage on the SSCB and solves the MOV reliability issue in the SSCBs. The presented SSCB employs a time-sequence control and needs no real-time detections of the dc current, which simplify the design. LTspice simulations of 380 V/80 A and 600 V/80 A are presented, and the results are compared with MOV- and MOV resistor–capacitor–diode (MOV-RCD)-based SSCBs. Also, experiments of a 380 V/80 A prototype validate the effectiveness of the proposed SSCB in practice where the voltage on the SSCB is clamped to 721 V with a fixed response time of 9.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> .

An Accurate Switching Transient Analytical Model for GaN HEMT under the Influence of Nonlinear Parameters

The Gallium Nitride high electron mobility transistor (GaN HEMT) has been considered as a potential power semiconductor device for high switching speed and high power density application since its commercialization. Compared with the traditional Si transistors, GaN HEMT has faster switching speed and lower on-off loss. As a result, it is more sensitive to the nonlinear parameters due to the fast switching speed. The subsequent voltage and current overshooting will affect the efficiency and safety of the GaN HEMT and power electronic systems. In this paper, an accurate switching transient analytical model for GaN HEMT is proposed, which considers the effects of parasitic inductances, nonlinear junction capacitances and nonlinear transconductance. The model characteristic of turn-ON process and turn-OFF process is illustrated in detail, and the equivalent circuits are derived for each switching transition. The accuracy of the proposed model can be verified by comparing the predicted switching waveform and switching loss with that of the experimental results based on the double pulse test (DPT) circuit. Compared with the conventional model, the proposed model is more accurate and matches better with the experimental results than the conventional model. Finally, this model can be used for analyzing the influences of gate resistance, nonlinear junction capacitances, and parasitic inductances on switching transient waveform and refining calculation switching loss.

Common-Mode EMI Mathematical Modeling Based on Inductive Coupling Theory in a Power Module With Parallel-Connected SiC MOSFETs

Parallelization of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) could significantly improve the current capability and power rating of power converters. However, the inductive coupling effect of parasitic inductance between the paralleled branches is a critical challenge for the mathematical modeling of electromagnetic interference (EMI) in a power module with parallel-connected SiC MOSFETs (PMPSM). In this article, first, an EMI source generation mathematical modeling method for PMPSM is proposed. The quantitative analysis of EMI interference source caused by inductive coupling of PMPSM is introduced. Second, a common mode (CM) interference propagation mathematical modeling method for PMPSM is proposed. Through the equivalent CM interference source and equivalent impedance model, the strong and weak inductive coupling theory of CM interference equivalent circuit based on parallel-connected SiC MOSFETs is proposed. Third the effect of different decoupling capacitance values on EMI source is compared and analyzed and the influence of changing the ratio of coupling inductance inside and outside the decoupling branch on EMI source of parallel-connected switches is analyzed. Finally, a self-made 1.2-kV 160-A PMPSM based on EMI optimized layout is proposed and tested via an experimental platform of synchronous buck converter, which can verify the feasibility and validity of the proposed power module and the theoretical analysis.

An Analytic Model for Predicting Single Event (SE) Crosstalk of Nanometer CMOS Circuits

With the technology node scaling down into nanometer range, the effect of parasitic inductance and capacitance between the interconnect lines on predicting single event crosstalk (SEC) has to be considered. An analytical model is proposed to evaluate SEC in nanometer CMOS circuits based on the equation circuit of single event transient and RLC distributed model of interconnect. The transfer function of the arbitrary segment of interconnects is deduced by applying KCL and KVL laws in Laplace domain. The accurate expression of SEC voltage is achieved by the operation of matrix polynomial. For convenient calculation, a third-order exponential model is used to describe the SEC voltage approximately. The simulation results at the technology nodes of 22 nm, 32 nm, 45 nm, 65 nm, and 90 nm show that in comparison to previous work, the analytical model has a significantly improved accuracy with an average error of only 2.19%.

Analysis and Design of a Low-Cost Well-Performance and Easy-to-Design Current Sensing Circuit Suitable for SiC mosfets

Current sense resistor (CSR) is widely used due to cost and integration considerations in industrial applications. However, when CSRs are used to sense transient currents caused by power device switching, especially fast-switching silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (mosfets) with high di/dt, even a tiny parasitic inductance in CSRs bring a significant impact on its sensing performance. This article proposes a low-cost well-performance and easy-to-design current sensing circuit that uses the CSRs and an LR compensation network (LRCN) to compensate for the effect of parasitic inductance on transient current sensing. In order to support the parameter selection of the LR network, the effects of parameters such as parasitic capacitance, parasitic inductance, and loads on the performance of the proposed current sensing circuit are analyzed in detail. Meanwhile, a parasitic inductance measurement method that only needs passive probes is proposed to measure and calculate the parasitic inductance of CSRs. This circuit can not only sense the transient current on the printed circuit board level but also observe the transient current on the oscilloscope through a coaxial cable connection. Finally, experimental studies under an inductive load double pulse test setup with SiC mosfets are carried out to verify the validity and feasibility of the proposed transient current sensing circuit. Only a high self-resonant frequency inductor and a surface mounted device resistor are needed to form the LR network to fully compensate the effect of parasitic inductance on CSRs.

Common-Mode Stability Test and Design Guidelines for a Transformer-Based Push-Pull Power Amplifier

We report design guidelines for a transformer-based push-pull power amplifier (PA) with a systematic stability test carried out in the complex frequency domain. By detecting the right half-plane zeros of the impedance matrix's determinant, the common-mode (CM) instability in a differential PA were accurately estimated with the established frequencies from the analysis. In the stability test, the parasitic series coupling capacitance of the input transformer and the parasitic inductance from the gate (base) biasing line were identified as the two primary mechanisms of the CM instability in a transformer-based PA contingent on stability. Based on the analysis of the instability mechanisms, useful stabilization methods were proposed and discussed for a robust push-pull PA design with a well-balanced performance. An onboard transformer-based push-pull PA was implemented for the verification purpose, and the effects of parasitic inductance on the stability had been investigated. The simulated and measured results corresponded well with the proposed analysis.

Circuit Design Considerations for Reducing Parasitic Effects on GaN-Based 1-MHz High-Power-Density High-Step-Up/Down Isolated Resonant Converters

With the availability of wide bandgap devices, the power converters can now potentially operate at megahertz (MHz) or higher frequencies while achieving ultrahigh efficiency. Such a high-frequency switching is particularly important for isolated converters to reduce the size of the passive components, achieve high power-density, and reduce costs. However, unlike the conventional kilohertz switching, in MHz switching, the parasitic components will significantly affect the circuit operation. These effects are compounded by high-ratio step-up or step-down isolated converters because the parasitic capacitances/inductances are squared times the turns’ ratio of the transformer when reflecting from high-voltage (HV) to low-voltage (LV) side to LV/HV side. In this paper, a high-step-up series resonant converter is used as a design example to explore the effects of parasitic inductances induced from the LV side and parasitic capacitances induced from the HV side on the circuit operation under MHz switching conditions. Afterward, the printed circuit board (PCB) layout and the planar transformer are optimized through the finite-element method to minimize the parasitic effects. Finally, a 1-MHz, 38-V/380-V, 300-W resonant converter prototypes are built and compared to verify the design optimization.

Electrical Performance and Reliability Characterization of a SiC MOSFET Power Module With Embedded Decoupling Capacitors

Integration of decoupling capacitors into silicon carbide (SiC) metal oxide semiconductor field effect transistor ( mosfet ) modules is an advanced solution to mitigate the effect of parasitic inductance induced by module assembly interconnects. In this paper, the switching transient behavior is reported for a 1.2-kV SiC mosfet module with embedded dc-link capacitors. It shows faster switching transition and less overshoot voltage compared to a module using an identical package but without capacitors. Active power cycling and passive temperature cycling are carried out for package reliability characterization and comparisons are made with commercial Si and SiC power modules. Scanning acoustic microscopy images and thermal structure functions are presented to quantify the effects of package degradation. The results demonstrate that the SiC modules with embedded capacitors have similar reliability performance to commercial modules and that the reliability is not adversely affected by the presence of the decoupling capacitors.

Suppression of Switching Crosstalk and Voltage Oscillations in a SiC MOSFET Based Half-Bridge Converter

The silicon carbide (SiC) MOSFET is characterized by high operating voltage, temperature, switching frequency and efficiency which enables a converter to achieve high power density. However, at high switching frequency, the crosstalk phenomenon occurs when the gate voltage spike introduced by high dv/dt and voltage ringing forces false turn-on of SiC MOSFET which causes a crow-bar current thereby increasing switching losses. In order to increase the immunity against the crosstalk phenomenon in a half-bridge configuration, this paper presents a gate driver for SiC MOSFET capable of generating the negative turn-off voltage without using a negative power supply. In addition, the effect of parasitic inductances on the switching response is analyzed and an RC snubber is designed using high-frequency based circuit reduction technique to dampen the switching ringing. The performance of the proposed gate driver and the designed RC snubber is validated using simulation and experiment at the 1 MHz switching frequency. The results show that the proposed gate driver with RC snubber eliminates crosstalk by maintaining any spurious gate spike below the gate threshold voltage.

Optically-activated cascode configuration for 650 V GaN FET devices and packaging parasitic inductance effects

In this paper, a novel optically-activated cascode structure is proposed to be used with a normally-on gallium nitride (GaN) field-effect transistor (FET) device to achieve an overall normally-off configuration. Using this novel configuration, cost-effective infrared (IR) lasers can be utilized instead of expensive ultraviolet (UV) lasers to activate this structure which includes a wide-bandgap-material device (GaN FET). Furthermore, the effect of parasitic inductance available in the package and connections of this proposed configuration is evaluated using Silvaco TCAD simulations. In practice, one high-power normally-on FET device is connected in series with a low-power optical switch (OS) to make the proposed overall normally-off cascode structure. The capability of being optically-activated for the proposed structure has many advantages over the conventional electrically-activated cascode structures including but not limited to: more immunity to electromagnetic interference (EMI), using only one main bias as the power source, using cost-effective long-wavelength laser instead of expensive short-wavelength lasers to trigger the GaN devices, reduced current and voltage ringing during switching transitions, etc. Comprehensive device modeling and parasitic inductance analysis for this new proposed optical cascode GaN FET device are provided in this work.

Active Gate Driving Technique for a 1200 V SiC MOSFET to Minimize Detrimental Effects of Parasitic Inductance in the Converter Layout

1200 V SiC mosfet is a suitable replacement for Si insulated gate bipolar transistors due to its improved switching behavior. However, high $di/dt$ and $dv/dt$ of SiC mosfet cause very high voltage overshoot and oscillations due to the presence of parasitic inductance in the converter layout and parasitic capacitance of the load. These undesired switching responses increase switching loss and give rise to electromagnetic interference related issues. Therefore, it is important to minimize these adverse effects in order to extract maximum benefits from SiC mosfet . This paper proposes an active gate driving technique for SiC mosfet to improve its overall switching performance in the presence of a moderately higher amount of parasitic inductance in the converter layout. It is achieved by controlling the device $di/dt$ and $dv/dt$ independently in four stages, with appropriate values of gate resistances for both turn- on and turn- off switching transient. The developed active gate driver is tested in a double-pulse test bed and a two-level voltage source inverter driving an induction motor load.

A class E GaN microwave power amplifier accounting for parasitic inductance of transistor

The effects of parasitic inductance of transistor on finite dc-feed inductance type class E microwave power amplifier is analyzed in this letter. We find that the frequency bandwidth can be improved by fully consideration of the output parasitic inductance of transistor. To validate the method, a GaN power amplifier by using the proposed topology is designed for demonstration purpose. Experimental results show that the amplifier is realized from 2.5 GHz to 3.5 GHz (33.3%) with measured drain efficiency larger than 60%, which show good agreement with the simulated results.

Correct extraction of frequency dispersion in accumulation capacitance in InGaAs metal-insulator-semiconductor devices

The anomalous frequency dispersion of the accumulation capacitance, i.e. an increase in the accumulation capacitance at high frequencies, of Pt/Al2O3/InGaAs metal-oxide-semiconductor (MOS) capacitors was investigated in this study. The anomalous frequency dispersion can be attributed to the considerable effects of parasitic inductance at high frequencies. The effects of parasitic inductance were effectively suppressed by decreasing the capacitor area without changing the MOS structure. This suggests that a smaller capacitor area should be used to precisely characterize the capacitance-voltage behavior of InGaAs-based MOS devices.

Cascode GaN HEMT를 적용한 위상 천이 dc-dc 컨버터의 구현 및 문제점 분석

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage () and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

Dynamic Real-Time I–V Curve Measurement System for Indoor/Outdoor Characterization of Photovoltaic Cells and Modules

A test method that measures the current-voltage I-V curve of a photovoltaic (PV) cell or module in real time is presented as a means of characterizing and understanding the inherently variable nature of performance under field conditions. Temperature, incident light intensity, orientation to the light source, incident spectrum, the uniformity of illumination, as well as a diverse set of failure mechanisms, both catastrophic and otherwise, have characteristic effects on the I-V curve. Seeing the I-V curve change dynamically with these influences allows visual correlation to real-time events. With a live I-V curve generated by performing forward and reversed bias sweeps repeatedly, the effect of parasitic inductance and bias sweep rate on the measurement can be demonstrated directly. This technique also ensures that the device junction is held in quasi-thermal equilibrium during the measurement. The relative alignment of optics in a concentrating photovoltaic module is analyzed to demonstrate the value of the live I-V curve.

Series-Connected Grounding of Common-Mode EMI Filter

Due to the effects of parasitic inductance, the common groundline (CGL) of capacitors in common-mode (CM) electromagnetic interference (EMI) filter is influential to filtration performance of the filter. In this paper, the effect of a single-point grounding method of CM EMI filter is first analyzed, and then, in order to eliminate the negative effect of CGL, a series-connected grounding method is introduced and analyzed. The effectiveness of the series-connected grounding method on improving the performance of CM EMI filter with CGL is verified through experiment.

Electric field-controlled sign of the capacitance in metal–carbon nitride–metal devices

Frequency and temperature dependent capacitance measurements were performed on metal–amorphous carbon nitride–metal sandwich structures. Negative capacitance effects occur under high electric field conditions for both polarities of the applied voltage. This low frequency behavior is shown to be incompatible with parasitic inductance effects. The dependence of negative apparent capacitance on frequency and temperature is discussed in the framework of field-assisted hopping transitions between localized states.

A new ZCZVT commutation cell for PWM DC-AC converters

This paper proposes a new auxiliary commutation cell for PWM inverters that allows the main switches to be turned on and off at zero voltage and zero current. The main switches zero current turn-on reduces the undesired effects of parasitic inductances related to the circuit layout. The main diodes reverse recovery losses are minimized since di/dt and dv/dt are controlled. The ZCZVT commutation cell is located out of the main power path of the converters and is activated only during switching transitions. Additionally, the auxiliary switches are turned on and off at ZCS and use the same ground signals of the upper main switches. The commutation losses are practically reduced to zero. Soft switching operation is guaranteed for full load range without changes in command strategy. The operation of the ZCZVT PWM full-bridge DC-AC Converter is analyzed and an auxiliary commutation cell design procedure based on the analysis is proposed. Experimental results are presented to demonstrate the feasibility of the proposed commutation cell.