Active Gate Driving Technique for a 1200 V SiC MOSFET to Minimize Detrimental Effects of Parasitic Inductance in the Converter Layout

Abstract

1200 V SiC mosfet is a suitable replacement for Si insulated gate bipolar transistors due to its improved switching behavior. However, high $di/dt$ and $dv/dt$ of SiC mosfet cause very high voltage overshoot and oscillations due to the presence of parasitic inductance in the converter layout and parasitic capacitance of the load. These undesired switching responses increase switching loss and give rise to electromagnetic interference related issues. Therefore, it is important to minimize these adverse effects in order to extract maximum benefits from SiC mosfet . This paper proposes an active gate driving technique for SiC mosfet to improve its overall switching performance in the presence of a moderately higher amount of parasitic inductance in the converter layout. It is achieved by controlling the device $di/dt$ and $dv/dt$ independently in four stages, with appropriate values of gate resistances for both turn- on and turn- off switching transient. The developed active gate driver is tested in a double-pulse test bed and a two-level voltage source inverter driving an induction motor load.