Modeling of switching behavior of 1200 V SiC MOSFET in presence of layout parasitic inductance

Abstract

1200 V SiC MOSFET is a viable alternative for state of the art Si IGBTs due to its superior switching performances. However, high di/dt and dv/dt during the switching transients worsen the switching performance of the SiC MOSFET due to the presence of parasitic inductances in the inverter layout. They cause undesired overshoot and oscillations in the device voltage and current. They also increase switching loss. These detrimental effects are required to be analyzed in detail to develop an efficient SiC MOSFET based inverter. In this paper, the effects of parasitic inductances on the switching performance of SiC MOSFET have been mathematically modeled. The modeling is verified with experimental results in a double pulse test circuit. Interestingly, the modeling reveals detrimental switching modes those can arise in the case of SiC MOSFET. They are highly unlikely to be observed in the case of Si IGBT.