Investigation of the effects of load parasitic inductance on SiC MOSFETs switching performance

Abstract

Parasitic inductances are responsible for oscillations and overshoots in the switching waveforms of SiC MOSFETs under high-frequency operations. In addition to the parasitic inductance of PCB board, bus-bar, device packaging, and drive circuit, the load inductance used for energy storage represents another source of parasitic inductance in SiC MOSFETs converters. Therefore, it is necessary to study the effect of the parasitic inductance contributed by inductive loads. This paper studies the effects of the load parasitic inductance on the switching performance of a SiC MOSFET-based switching power pole (SPP) or what traditionally defined as a half-bridge. The goal is to identify the influence of the load parasitic inductance on the overshoot and ringing in the waveforms of the device drain-to-source voltage and drain current. Using a simple procedure based on experimental measurements of the device drain-to-source voltage and drain current along with the mathematical formula of the inductance, the value of the parasitic inductance of the load inductor was evaluated.