Effect Of Interface Trap Charges Research Articles

Reduced OFF-state current and suppressed ambipolarity in a dopingless vertical TFET with dual-drain for high-frequency circuit applications

In this article, a dopingless TFET with dual-drain and reversed T-shaped channel (DLVIT-TFET) is investigated to offer improvement in ON-state current (IOn) along with the reduction in OFF-state leakage current (IOff) and in ambipolarity. The investigated device has a dual channel region which helps in improving the on-state parameters like IOn and subthreshold swing (SS) due to the extended tunneling area. The inverted T-shaped channel minimizes the charge carriers to tunnel during the off-state, thereby reducing the magnitude of IOff. The results obtained from 2D TCAD simulation show that the investigated device provides ∼1 order of improvement in IOn and ∼3 orders of improvement in IOff. Furthermore, DLVIT-TFET offers an ∼3 orders of improvement in ambipolar current (IAmb) due to a reduction in peak electric field at channel-drain interface caused by splitting of drain potential at ambipolar state. Moreover, various analog/RF parameters such as transconductance (gm), gate parasitic capacitance (Cgd, and Cgs), cut-off frequency (fTmax), gain-bandwidth product (GBP), transconductance-frequency product (TFP) and transit time (τ) are found to be improved in DLVIT-TFET compared to the conventional DL-TFET. In addition, the transient analysis of DLVIT-TFET based inverter is analyzed, which shows improvement in the parameters like propagation delay and voltage swing. Finally, reliability of the investigated device is discussed by considering the effect of interface trap charges (ITCs) and variation in ambient temperature and it is observed that DLVIT-TFET is more immune to such defects and environmental factors than the conventional one.

Effect of ITC on Boolean functionality of n-type heterojunction vertical TFETs

The objective of this paper is to investigate the effect of interface trap charges (ITC) on Boolean functionality of n-type vertical TFET structure with and without gate overlap (HJ-VTFET-WG and HJ-VTFET-WOG). For this, the logic gates are designed using HJ-VTFET by considering germanium as source material. Our simulations results have shown that two input logic functions such as AND and OR gates can be successfully implemented using HJ-VTFET-WG and HJ-VTFET-WOG structures. The two key concepts are utilized for achieving logic functionality of proposed vertical TFET such as change in gate–source overlap area and appropriate selection of silicon body thickness. Thereafter, the AND and OR functionality are examined using drain current characteristic and energy band diagram of HJ-VTFETs under different trapped charges. With positive ITC, the logic functions have a smaller tunneling width and a larger tunneling width with negative ITC. It is found that positive ITCs can improve device features, whereas, negative ITCs degrade device performance. Further, the electrical performance of HJ-VTFET-WG is less susceptible to interface trap charges than HJ-VTFET-WOG which indicates that the proposed HJ-VTFET-WOG structure is a potential candidate for designing the logic gates for digital application under ITC effect.

Investigation on Effect of Interface Trap Charges and Temperature in Gate Overlap Graphene Source Step Shape Double Gate Tunnel FET

Abstract This work evaluates the electrical parameters of Gate Overlap Graphene source Step Shape Double Gate TFET (GO-GR-SSDG-TFET) with wide variation in interface trap charges (ITCs) and temperature. Here, both the positive interface charges (PITCs) and negative interface charges (NITCs) along with temperature ranges from 200-500 K on DC, RF/analog and linearity characteristics are analyzed using TCAD Sentaurus Simulator. It is observed that there is improvement (degradation) in current ratio, transconductance, gain, cut-off frequency, and delay with increase (decrease) in PITC (NITC), whereas, opposite trend is realized in terms of linearity parameters. The rise in temperature leads to degradation is subthreshold behaviour due to exponential characteristic of Shockley-Read-Hall (SRH) recombination with temperature. It is also seen that at high temperature there is degradation transconductance, device efficiency, cut-off frequency, current ratio, delay, and temperature sensitivity (ST) in the proposed TFET. Moreover, the linearity parameters are degraded with rise in temperature. Finally, a comparison table is highlighted in terms of various electrical parameters for proposed TFET with existing data.

Modeling and simulation assessment of dual material gate Delta(δ) doped fully depleted SOI-FET with effect of interface trap charges

A two–dimensional (2D) analytical model with surface potential changes in the delta doped dual material gate with fully depleted silicon on insulator-MOSFET (DMG-DD-SOIFET) is designed to evaluate device characteristics in consideration of interface trap charges (InTCs). The present paper introduced a novel δ-doped in SOIFET to improve device performance. The potential is modeled via two-dimensional Poisson's equations and interface trap charges (InTCs) impact which is verified with numerical simulations using TCAD tool of Silvaco ATLAS. Further, a parametric investigation is carried out to adjust the dimensions of device for a nano-scaled MOS architecture. The performance investigation model and simulation work also involve the calculation of surface potential, drain current and threshold voltage comprising effects of InTCs. It is found that the proposed DMG-DD-SOIFET suggests excellent immunity for short-channel-effects (SCEs) in addition to better device performance for different InTCs conditions.

DC and RF/analog performances of split source horizontal pocket and hetero stack TFETs considering interface trap charges: A simulation study

This work investigates the impact of different types of interface trap charges (ITCs) on electrical parameters of split source horizontal pocket Z shape TFET (ZHP-TFET) and Hetero Stack TFET (HS-TFET) using TCAD simulator. The acceptor type Uniform/Gaussian ITCs are considered at the oxide and semiconductor material interface. The effect of ITCs on transfer characteristics, energy band diagram (at ON, OFF, and ambipolar states), electron density, electron velocity, recombination rate, and electric field are reported for both the TFETs. Furthermore, the various RF/analog parameters like transconductance (gm), gate capacitance (CGG), cut-off frequency (fT), transconductance generation factor (TGF), and transconductance frequency product (TFP) are highlighted in the presence of ITCs for both the structures of TFET. Finally, the linearity parameters like VIP2, VIP3, IIP3, and IMD3 are extracted considering ITCs for both the structures. Simulation result reveals that the various DC, RF/analog, and linearity parameters in ZHP-TFET are more immunes towards different types of ITCs than HS-TFET. It is seen that ZHP-TFET is favorable in terms of DC and RF/analog performances compared to HS-TFET, even in the presence of ITCs. Moreover, a comparative study of various Figure of Merits (FoMs) for ZHP-TFET with existing literature is presented.

Detection of SARS-CoV-2 using dielectric modulated TFET-based biosensor.

Attributable to the rapid increase in human infection of Coronavirus disease 2019 (COVID-19) caused by severe acute respiratory syndrome coronavirus-2 (SARS-CoV-2), the World Health Organization (WHO) has declared this disease outbreak as a pandemic. This outbreak can be tackled to some extent through proper management and early diagnosis. This work reports a biosensor based on vertical tunnel field-effect transistor (VTFET) developed for the detection of SARS-CoV-2 from the clinical samples through the analysis of its spike, envelope, and DNA proteins. Investigation of the sensitivity of the proposed sensor has been done by calculating the shift in drain current. The dielectric constant equivalent of the virus proteins is used to represent the hybridized biomolecules within the nanogaps. The sensitivity of this proposed sensor is found to be significantly high (order of 106) showing the viability of the device to be a superior sensor. Furthermore, the sensitivity analysis concerning DNA charge density is also performed. The effect of DNA charge density variation on the threshold voltage (Vth) and sensitivity have also been studied in this work. The proposed sensor is also investigated for its noise performance and observed the sensitivity with and without the effect of interface trap charges. Finally, the proposed sensor is benchmarked against the sensitivity of various FET-based biosensors already published earlier.

A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET

In this work, the impact of interface trap charges (ITCs) on electrical characteristics of dielectric pocket SOI-TFET (DP SOI-TFET) proposed for the reduction of ambipolar conduction and improvement of high-frequency (HF) performances has been demonstrated in details. The reliability of DP SOI-TFET has been examined by analysing the impact of varying polarity and density of ITCs on dc and analog/HF performances of the proposed device. Through TCAD simulations, it has been shown that donor and acceptor ITCs existing at the interface between drain region and dielectric pocket (i.e. Si/DP) have significant impact on the parameters such as OFF-state current, ambipolar conduction, parasitic capacitances, output resistance, and cut-off frequency of DP SOI-TFET. Furthermore, a comparative analysis has been carried out between the conventional and DP SOI-TFET under influence of traps, and it has been found that performances of the proposed device are further improved by the existence of acceptor ITCs at higher negatively biased gate. Even though, the existence of donor ITCs at Si/DP interface has been found degrading the performances of the proposed DP SOI-TFET, simulation results suggest that dc and analog/HF figure of merits are still superior in the proposed device as compared to those in the conventional SOI-TFET.

Investigation of interface trap charges and temperature variation in heterostacked-TFET

This paper analyzes the reliability issues of the Heterostacked-TFET (HS-TFET) in detail. The investigation of the device reliability is carried out by examining the effect of interface trap charges (ITCs) and the temperature affectability of the HS-TFET on various analog parameters and RF FOMs. The analysis is performed at different interface trap charge densities and polarities. The presence of interface traps at the stackedsource/channel junction and the oxide/silicon interface alters the performance of the device significantly. A positive trap charge density of 3 × 1013 cm−2 degrades the current switching ratio tremendously from an order of 1010–104. The off-state current of the device deteriorates excessively at high temperatures. However, the results establish that the HS-TFET is insusceptible to the acceptor interface trap charge as compared to the donor interface trap charge for temperature variation. A high-k gate dielectric of Aluminum oxide (Al2O3) is considered and compared with Hafnium oxide (HfO2) and it is found that Al2O3 gate oxide has a better immunity to the ITC variation.

Effect of ITCs on gate stacked JL‐TFET based on work‐function engineering

A stacked double gate junctionless tunnel field-effect transistor (JL-TFET) has been proposed and examined the effects of interface trap charges (ITCs) by introducing both acceptor and donor charges at the semiconductor/insulator interface. The structure uses two isolated gates (polarity gate and control gate) over an n-type-doped silicon substrate to function as a TFET. The effect of ITCs has been analysed in terms of DC and analogue/radio-frequency performance using parameters such as transfer characteristics, electric field, electric potential, transconductance (g m) for both conventional and gate stacked JL-TFET. Additionally, they have also analysed metrics used to measure the device linearity performance and intermodulation distortion such as higher-order transconductance coefficients (g m2, g m3) and figure of merit. All the simulations have been performed with the help of an Atlas device simulator.

Effect of interface trap charges on the performance of asymmetric dielectric modulated dual short gate tunnel FET

In this paper, the influence of interface trap charges on the characteristics of asymmetric dielectric modulated dual short gate tunnel field effect transistor (ADMDG-TFET) has been analyzed. The effect of a donor (positive) and acceptor (negative) trap charges with various concentrations on the device d.c characteristics are studied. A comparative analysis has been performed between symmetric silicon dual gate tunnel field effect transistor (DG-TFET) and ADMDG-TFET (both Si and Si0.3Ge0.7) with matching dimensions in the presence/absence of interface trap charges. It is found that a shift in threshold voltage (Vth) and subthreshold swing (SS) degradation are observed due to the presence of interface traps in both devices. However, the ADMDG TFET is more immune to Vth shift and SS degradation by acceptor and donor interface traps compared to silicon DG TFET. Also, the ambipolar current in ADMDG TFET is more suppressed than the silicon DG TFET in the presence of trap charges.

Reliability Issues of In2O5Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature

In this paper, reliability issues of In2O5Sn (indium–tin oxide: a transparent material) transparent gate recessed channel (TGRC)-MOSFET has been analyzed by considering the effect of interface trap charges (both positive and negative) present at the Si/SiO2 interface. Following device, characteristics are studied in terms of static, linearity, and intermodulation figure of merits. It is found that with the amalgamation of the transparent gate indium tin oxide on conventional recesses channel (CRC) MOSFET, it exhibits improved immunity against interface trap charges in comparison to CRC-MOSFET. In addition, the influence of ambient temperature (150–300 K) along with trap charges on TGRC-MOSFET has also been explored with an aim to analyze at which temperature of the device is more stable in the presence of interface defects (trap charges). Results obtained reveal that TGRC shows improved device performance at low temperature with trap charges being less influenced. Thus, this paper demonstrates that TGRC MOSFET can act as a promising candidate for low-power linear analog applications, where low temperature is required.

Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET

In this paper, we investigate the effect of interface trap charges on the variation of heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor and acceptor type of localized charges at the semiconductor/insulator interface. In this regard, we have analyzed dc and analog/RF performance parameters for conventional and heterogeneous gate dielectric JL-TFET (HD JL-TFET) in terms of electric field, transfer characteristics, transconductance ( ${g}_{m}$ ), output transconductance ( ${g}_{\text {ds}}$ ), parasitic capacitances, device efficiency, cutoff frequency ( ${f}_{T}$ ), gain bandwidth product, and transconductance frequency product. Apart from these, linearity distortion parameters are also analyzed in the form of higher order transconductance coefficients ( ${g}_{m1}$ , ${g}_{m2}$ , ${g}_{m3}$ ), VIP2, VIP3, IMD3, and IIP3. For this, high-K gate dielectric material (HfO2) is used in the case of the HD JL-TFET to improve the performance of the device. All the simulations for both devices have been performed with the help of an ATLAS device simulator.