Edge Termination Technique Research Articles

Optimisation of Negative Fixed Charge Based Edge Termination for Vertical GaN Schottky Devices.

This study focuses on the impact of negative fixed charge, achieved through fluorine (F) implantation, on breakdown voltage (BV) enhancement in vertical GaN Schottky diodes. Several device and implant-related parameters are examined using Synopsys Sentaurus TCAD simulations in order to determine the optimum fixed negative charge concentration required to achieve the highest BV. The simulated structure consisted of a Schottky diode with a box consisting of negative fixed charges to achieve the edge termination of the Schottky device. An empirical equation is proposed to determine the optimum fixed charge concentration for the highest BV based on depth. The simulation also considered implantation profiles derived from SIMS data from an actual device implanted with multi-energy and multi-dose F. It is demonstrated that the BV has a similar dependence on the key parameters like in the box profile. In summary, this work provides valuable insights into optimizing edge termination techniques using negative fixed charge for improved BV in vertical GaN power devices.

P-GaAs/n-Ga2O3 heterojunction diode with breakdown voltage of ∼800 V

As an attractive next generation ultrawide bandgap material, Ga2O3 has been demonstrated to be capable of high voltage operation. However, the lack of shallow p-type dopant in Ga2O3 leads to difficulties in developing Ga2O3 based bipolar devices. The semiconductor grafting technology, by bonding a single crystalline p-type semiconductor nanomembrane (NM) to n-Ga2O3 to from abrupt heterojunction, offers a way to expand the application of Ga2O3 in bipolar areas. In this Letter, we report a p-GaAs/(001)-Ga2O3 heterojunction diode fabricated using semiconductor grafting technology. The single crystalline GaAs NM was prepared and transferred onto a Ga2O3 substrate, showing good integrity. Diodes of a mesa diameter of 25 μm were fabricated, showing a high breakdown voltage of ∼800 V, a power figure of merit of 126.5 MW/cm2, and a calculated 1D peak electric field of 1.60 MV/cm. The turn on voltage of the diode was determined to be around 1.91 V with an on–off ratio to be 6 × 106 at −4/4 V and the specific on resistance to be 5.06 mΩ cm2. The ideality factor was extracted to be approximately 1.34, indicating reasonable interface quality. The interfacial defects and the self-passivation effects of Ga2O3 are discussed, and the theoretical band diagram was analyzed for the p-GaAs/n-Ga2O3 heterojunction. By managing the peak electric field with suitable edge termination techniques, higher breakdown voltage can be expected. In addition, by taking advantage of the InGaAsP alloy system, a wide variety of GaAs-Ga2O3 based high voltage HBT can be further developed.

Trench edge termination in a GaN-based power device

The comfort of the modern society is somehow relied on production of high voltage and high frequency devices. Being mature in performance, wide bandgap semiconductors have replaced silicon-based devices. However, wide bandgap semiconductor devices are plagued with their premature breakdown, which owes to edge effects. Present work demonstrates breakdown voltage enhancement in GaN based Schottky diode using trench edge termination technique. Al 2 O 3 was filled in the trench of the structure. The atlas module of the Silvaco TCAD software has been used to replicate the device structure. Numerous models for ionization, recombination, impact ionization and mobility have been used. The breakdown voltage of the device is estimated to be 350 V due to the increase in the electric field at the edges. Using trench termination, the edge electric field crowding has been found spreading away from the edges of the device and in the Al 2 O 3 layer. As a consequence, the trench edge terminated device has a reverse breakdown voltage increased to 1800 V.

A Simple Edge Termination Design for Vertical GaN P-N Diodes

Vertical power devices require significant attention to their edge termination designs to obtain higher breakdown voltages without substantial increase in ON-state resistance. A simple edge termination structure for a GaN p-n diode is proposed, comprising a full layer lightly doped p-type GaN region underneath the higher doped <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p} +\!+$ </tex-math></inline-formula> contact layer. A TCAD model of the device is developed, and removal of the portions of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ++ cap outside of the device active area in simulations is shown to increase the device blocking voltage capability. It causes the depletion width to increase in the lightly doped p-type layer and allows it to act similar to a junction termination extension (JTE). These predictions are validated empirically, resulting in a 52% measured increase in breakdown capability after selective removal of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ++ cap. This simple edge termination technique can be formed with only a single low-energy nitrogen implant or etching procedure, greatly increasing its manufacturability over more complex structures. Design optimization studies are pursued in TCAD to determine optimal parameter values for further improving breakdown performance. It is shown that the proposed edge termination technique can be employed to produce future high voltage vertical GaN devices without a significant gain in ON-state resistance and with wide tolerance to process variations.

Modeling and Optimization of Smoothly Tapered Junction Termination Extension for High-Voltage SiC BJTs and Thyristors by Simulation

Based on a newly proposed edge termination technique on silicon carbide (SiC) device named aperture density modulation (ADM), this article investigates the optimization strategy of a family of termination structures derived from it. Using both analytical modeling and numerical simulation, this article demonstrates the capability of achieving 15-kV breakdown voltage with a termination length of 160–240 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> in theory. Besides, the fabrication feasibility with profile customizability is also demonstrated in experiments while still keeping a low process cost.

Implantation-free edge termination structures in vertical GaN power diodes

Gallium nitride (GaN) is a promising candidate for power applications, due to its superior electrical properties such as high critical breakdown field and saturation drift velocity. The recent emergence of GaN substrates with low defect densities has made it feasible to develop efficient vertical GaN power diodes. However, the breakdown voltage of these diodes is far from the theoretical value, due to the lack of suitable edge termination techniques in GaN such as junction termination extension (JTE). This is attributed to the processing challenges in fabricating GaN power diodes where it is difficult to form p-type regions through implantation. This work addresses this challenge and proposes the design, optimization, and a comprehensive design methodology for implantation-free, edge termination techniques such as field plate (FP), single and multi-etch JTE, and a hybrid FP-JTE structure, suitable for vertical GaN diodes. The proposed approaches demonstrate that close to theoretical breakdown voltages (>80%) are achievable, with greater area efficiency, simple processing, and high tolerance in process variation.

Edge-Termination Technique for High-Voltage Mesa-Structure 4H-SiC Devices: Negative Beveling

The prospects for the protection of high-voltage 4H-SiC-devices from edge breakdown via the formation of mesa structures with inclined walls (negative beveling) are considered. Numerical simulation of the spatial electric-field distribution in high-voltage (~1500V) reverse-biased mesa-epitaxial p+–p–n0–n+ 4H-SiC diodes is performed. It is shown that negative beveling with small angles of less than 10° from the plane of the p–n0 junction makes it possible to reduce severalfold the surface edge electric field as compared to that in the bulk. A combined protection method is suggested as the edge-termination technique for 4H-SiC diodes with a p+–n0–n+ structure, Schottky diodes with an n0 blocking base, and bipolar n+–p–n0 transistors via the implantation of boron along with negative beveling. The possibility of fabricating mesa structures with inclined walls via the photolithography and dry etching of silicon carbide is briefly discussed.

Beveled Fluoride Plasma Treatment for Vertical $\beta$ -Ga2O3Schottky Barrier Diode With High Reverse Blocking Voltage and Low Turn-On Voltage

In this letter, we report on demonstrating a high performance vertical $\beta $ -Ga2O3 Schottky barrier diode (SBD) based on a self-aligned beveled fluorine plasma treatment (BFPT) edge termination structure. Owing to the strong electronegativity of fluorine ions, the fixed negative charges introduced by F ions during self-aligned BFPT process alleviate the electric field crowding, reduce the reverse leakage current and improve the breakdown voltage up to 1 050V even with a low differential on resistance of 2.5 $\text{m}\Omega \cdot $ cm2, combining with a high $I_{\text {on}}/I_{\text {off}}$ of 109, a Schottky barrier height of 1.03 eV and a low ideality factor of 1.07-1.11.Without implantation and post annealing, the self-aligned BFPT can serve as a simple, effective and viable edge termination technique to fabricate high performance $\beta $ -Ga2O3 rectifiers.

Multizone Gradient-Modulated Guard Ring Technique for Ultrahigh Voltage 4H-SiC Devices With Increased Tolerances to Implantation Dose and Surface Charges

An area efficient multizone gradient-modulated guard ring (MGM-GR) edge termination technique is proposed, fabricated, and analyzed for 10-kV class silicon carbide devices without extra process steps or masks, which provides a better tradeoff between near ideal blocking capabilities and technological process complexity. The edge termination region is divided into multiple zones by employing MGM-GR technique, which forms a similar linearly graded doping profile to relieve the amount of electric field crowding at the periphery of the active area and achieve a maximum blocking voltage with wide tolerance to implantation dose. The proposed device shows not less than a 35% reduction in edge termination area in comparison with a conventional equally spaced ring at a breakdown voltage of 10 kV. Moreover, MGM-GR shows good tolerances to breakdown voltage for total implant dose and interface charges. With the application of MGM-GR technique to SiC MOSFET with a 100- $\mu \text{m}$ -thick N− epilayer doped to $5 \times 10^{14}$ cm $^{-3}$ , the measured breakdown voltage is 13.6 kV at $10~\mu \text{A}$ . This voltage is nearly 95% of the theoretical value calculated for a 1-D structure. Simulated and measured characteristics show that MGM-GR structure is a candidate for an ultrahigh voltage power device to maximize power density and driving down system complexity.

Diamond Schottky barrier diodes with floating metal rings for high breakdown voltage

Investigation of influence of floating metal rings (FMRs) edge termination technique on the breakdown voltages of diamond Schottky barrier diodes (SBDs) has been carried out. Unintentionally doped P- drift layer was grown on HPHT boron doped diamond substrate by microwave plasma CVD system and treated by ultraviolet ozone. Then, Ti/Ni/Au electrode was deposited on the back side of the substrate to form ohmic contact. Zr/Ni/Au Schottky electrodes with different FMRs parameters, such as ring spacing (RS), ring width (RW) and ring number (RN), were deposited on the P- layer. The I–V measurement results show that breakdown voltages increase firstly and then decease with increasing of RS. The increases of RW and RN are beneficial to improve breakdown voltages. Moreover, FMRs structure can effectively improve breakdown voltages without deteriorating forward current density and rectification ratio of diamond SBDs.

Optimization of Edge Termination Techniques for β-Ga2O3 Schottky Rectifiers

To realize the potential of Gallium oxide (Ga2O3) Schottky rectifiers fabricated for high voltage and fast switching applications, various edge termination techniques to maximize the breakdown voltage (Vbr) are studied and examined via simulations using the FLOODS/FLOOPS TCAD simulator. The simulated Schottky rectifiers consist of a Si-doped (n = 1.0 × 1015 – 1.3 × 1017 cm−3) β-Ga2O3 epitaxial layer grown on Sn-doped (n = 4.8 × 1018 cm−3) Ga2O3 substrates. The optimization of field plate geometry for Schottky barrier diodes (SBD) was investigated using the device breakdown characteristics as the figure-of-merit. Various field plate dielectrics (SiO2, SiNx, Al2O3, and HfO2) were explored while the field plate structure was concurrently varied to obtain a normalized breakdown field (VNbr) of ∼3 for a step (graduated form) dielectric with Al2O3 as the dielectric. Edge termination via the formation of resistive areas at the anode contact periphery via ion (argon) implantation was also examined for the SBDs since other edge termination techniques are ineffective due to lack of p-type doping in Ga2O3. The configuration of the implanted region was investigated and a VNbr of over 5 was achieved for diodes with an unbounded resistive region and an implantation depth of 50–100 nm.

A simple multistep etched termination technique for 4H-SiC GTO thyristors

An edge termination technique, referred to as simple multistep etched junction termination extension (SME-JTE), is presented for 4H-silicon carbide gate turn-off thyristors (4H-SiC GTO). The proposed termination technique can form over ten steps in the termination region with only requiring a few of etching steps. Numerical simulations show that a high termination efficiency over 95% with broad process window for etching depth is obtained for the SME-JTE technique. In addition, a high breakdown voltage of 7500 V has been experimentally demonstrated for the 4H-SiC GTO with 8-step JTE, and which is about 91% of the ideal breakdown voltage for the 50 μm drift layer. The high termination efficiency and simple process of SME-JTE makes it applicable for fabrication of various high-voltage power devices.

High Performance Vertical GaN-on-GaN p-n Power Diodes With Hydrogen-Plasma-Based Edge Termination

This letter reports the first implementation of a hydrogen-plasma-based edge termination technique (HPET) in vertical GaN p-n power diodes grown on bulk GaN substrates using metalorganic chemical vapor deposition. The device with a 9- $\mu \text{m}$ -thick drift layer exhibited a high breakdown voltage ( ${V}_{\textsf {bd}}$ ) of 1.57 kV, a low ON-resistance ( ${R}_{\mathrm{ ON}}$ ) of 0.45 $\text{m}\Omega ~ \cdot $ cm2 (or 0.70 $\text{m}\Omega ~\cdot $ cm2 with current spreading considered) and a high Baliga’s figure-of-merit ( ${V}^{\textsf {2}}_{\textsf {bd}}/{R}_{\mathrm{ ON}}$ ) of 5.5 GW/cm2 (or 3.6 GW/cm2) without passivation or field plate, which are close to the theoretical limit of GaN. This technique enabled a significant reduction in leakage current (~106 times at −300 V) and a huge enhancement in ${V}_{\textsf {bd}}$ (from ~300 V to 1.57 kV). Furthermore, the device showed good forward characteristics with a turn-ON voltage of 3.5 V, an ON-current of ~2 kA/cm2 (or 1.3 kA/cm2), an ON/OFF ratio of ~109, and an ideality factor of 1.4. This work shows the HPET can serve as an effective, low cost, and easy-to-implement edge termination technique for high voltage and high power GaN p-n power diodes.

Design and Fabrication of 1400V 4H-SiC Accumulation Mode MOSFETs (ACCUFETs)

This paper presents design, fabrication, and electrical performance of 8A, 1400V 4H-SiC ACCUFETs. It is intended to provide detail discussions on channel design, edge termination technique, and electrical characteristics of high current, 1.2kV rated 4H-SiC ACCUFETs.

A Comparative Study 4500-V Edge Termination Techniques for SiC Devices

This paper compares five edge termination techniques for SiC high-voltage devices: single zone junction termination extension (JTE), ring assisted-JTE (RA-JTE), multiple floating zone-JTE, hybrid-JTE, and floating field rings. PiN diodes with these edge terminations were fabricated on a 4.5kV-rated 4H-silicon carbide (4H-SiC) epi-layer. It was experimentally demonstrated that the Hybrid-JTE provides a nearly ideal breakdown voltage (~ 99% of the ideal parallel plane breakdown voltage) with a stable avalanche blocking behavior. RA-JTE, with tight control of the JTE implant dose, is demonstrated to be the most area-efficient edge termination structure for SiC power devices.

A Near Ideal Edge Termination Technique for 4500V 4H-SiC Devices: The Hybrid Junction Termination Extension

This letter presents a new edge termination technique named a hybrid junction termination extension (Hybrid-JTE), which combines ring-assisted JTE and multiple floating zone JTE. Based on the parameters of the drift layer specified by the wafer vendor, the measured breakdown voltage of the fabricated p-i-n diode using the Hybrid-JTE is as high as 5450 V, which is close (~99%) of the ideal parallel plane p-n junction. Furthermore, measured breakdown voltages from randomly chosen 32 p-i-n diodes across the wafer show very tight distribution: 29 diodes provide breakdown voltages higher than 5000 V at $100~\mu \text{A}$ .

Development of 17 kV 4H-SiC PiN diode**Project supported by the National High Technology Research and Development Program of China (No. 2014AA041401).

The design, fabrication, and electrical characteristics of a 4H-SiC PiN diode with breakdown voltage higher than 17 kV are presented. The three-zone JTE has been used in the fabrication. Numerical simulations have been performed to optimize the parameters of the edge termination technique. The epilayer properties of the N-type are 175 μm with a doping of 2 × 1014 cm−3. With the three-zone JTE, a typical breakdown voltage of 17 kV has been achieved.

DLTS analysis of high resistive edge termination technique‐induced defects in GaN‐based Schottky barrier diodes

Efficient edge terminations are fundamental for power electronic devices. High resistive edge termination technique obtained by ion implantation is a possible solution for GaN Schottky barrier diodes (SBD), but may induce defects detrimental to the devices. In this work, two sets of GaN SBDs, with or without a high resistive guard ring edge termination, were investigated by deep levels transient spectroscopy (DLTS). The corresponding DLTS spectra of devices with guard ring were compared to those of as‐fabricated devices (without). Four deep traps at 0.13, 0.26, 0.35, and 0.51 eV were observed below the conduction band in as‐fabricated structures while the ones with guard ring exhibit two additional levels at 0.47 and 0.80 eV and a strong enhancement in DLTS peaks magnitude. Further investigations showed that the additional traps detected in SBD devices with guard ring were consistent with ion implantation‐induced damages. These observations highlight the impact of high resistive edge termination technique on our devices and raise the need of optimization of such crucial structure for the improvement of GaN‐based Schottky barrier diode.

4H-SiC 소자의 JTE 구조 및 설계 조건 변화에 따른 항복전압 분석

Silicon Carbide(SiC) has large advantage in high temperature and high voltage applications because of its high thermal conductivity and large band gap energy. When using SiC to design power semiconductor devices, edge termination techniques have to be adjusted for its maximum breakdown voltage characteristics. Many edge termination techniques have been proposed, and the most appropriate technique for SiC device is Junction Termination Extension(JTE). In this paper, the change of breakdown voltage efficiency ratio according to the change of doping concentration and passivation oxide charge of each JTE techniques is demonstrated. As a result, the maximum breakdown voltage ratio of Single Zone JTE(SZ-JTE), Double Zone JTE(DZ-JTE), Multiple Floating Zone JTE(MFZ-JTE), and Space Modulated JTE(SM-JTE) is 98.24%, 99.02%, 98.98%, 99.22% each. MFZ-JTE has the smallest and SZ-JTE has the largest sensitivity of breakdown voltage ratios according to the change of JTE doping concentration. Additionally the degradation of breakdown voltage due to the passivation oxide charge is analyzed, and the sensitivity is largest in SZ-JTE and smallest in MFZ-JTE, too. In this paper, DZ-JTE and SM-JTE is the best efficiency JTE techniques than MFZ-JTE which needs large doping concentration in short JTE width.

Counter-Doped JTE, an Edge Termination for HV SiC Devices With Increased Tolerance to the Surface Charge

In this paper, a comparison of different techniques for SiC high-voltage devices is performed using numerical simulations. In particular, the method of counter doping (CD) introduced in the junction termination extension (JTE) region to create a multizone termination effect is investigated. Simulation shows that compared with the other edge termination techniques, CD-JTE greatly reduces the sensitivity of breakdown voltage (BV) to JTE doses and surface charges. The multizone CD-JTE with outer rings shows that for a 30-μm thick epi-layer, 90% of the theoretical BV is achievable with a wide tolerance of 11 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to the JTE dose and 85% of the theoretical BV with an increased tolerance of 6.19 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to the positive surface charges, both superior to other JTE structures investigated in this paper.