Edge Placement Error Research Articles

Mask-filtering-based inverse lithography

We propose a new regularization framework for inverse lithography that regularizes masks directly by applying a mask filtering technique to improve computational efficiency and to enhance mask manufacturability. This technique is different from the conventional regularization method that regularizes a mask by incorporating various penalty functions to the cost function. We design a specific mask filter for this purpose. Moreover, we introduce a metric called edge distance error (EDE) to guide mask synthesis and establish the correlation between pattern error and edge placement error (EPE) via EDE. We prove that EDE has the same dimension as EPE and has a continuous expression as pattern error. Simulation results demonstrating the validity and efficiency of the proposed method are presented.

Litho-Friendly Decomposition Method for Self-Aligned Double Patterning

This paper establishes self-aligned double patterning (SADP) decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the SADP-specific printability requirements that should be considered during decomposition. In silico experiments indicate that layout patterns that are printed by the trim mask may experience the highest levels of image distortion. Therefore, these patterns should be assisted by sidewalls of spacer patterns to improve printing robustness. Next, we present an integer linear programming-based decomposition method that avoids decomposition conflicts and sensitive trim edges simultaneously. To improve runtime and extend its application to partially decomposable layouts, too, a partitioning-based decomposition is also proposed. Our experiments reveal that the proposed methods decrease the total length of sensitive trim patterns and consequently reduce the total edge placement error significantly.

Level-set-based inverse lithography for mask synthesis using the conjugate gradient and an optimal time step

Inverse mask synthesis is achieved by minimizing a cost function on the difference between the output and desired patterns. Such a minimization problem can be solved by a level-set method where the boundary of the pattern is iteratively evolved. However, this evolution is time-consuming in practice and usually converges to a local minimum. The velocity of the boundary evolution and the size of the evolution step, also known as the descent direction and the step size in optimization theory, have a dramatic influence on the convergence properties. This paper focuses on developing a more efficient algorithm with faster convergence and improved performance such as smaller pattern error, lower mean edge placement error, wider defocus band, and higher normalized image log slope. These improvements are accomplished by employing the conjugate gradient of the cost function as the evolution velocity, and by introducing an optimal time step for each iteration of the boundary evolution. The latter is obtained from an extended Euler time range by using a line search method. The authors present simulations demonstrating the efficacy of these two improvements.

Fast aerial image simulations for partially coherent systems by transmission cross coefficient decomposition with analytical kernels

Aerial image simulation is one of the most critical components in the model-based optical proximity correction (OPC), which has become a necessary part of resolution enhancement techniques used to improve the performance of subwavelength optical lithography. In this paper, a fast aerial image simulation method is proposed for partially coherent systems by decomposing the transmission cross coefficient (TCC) into analytical kernels. The TCC matrix is projected onto a function space whose basis is analytical circle-sampling functions (CSFs) and converted into a much smaller projected matrix. By performing singular value decomposition (SVD) to the projected matrix, its eigenvectors together with the CSFs are used to generate a set of analytical TCC kernels. The proposed method avoids directly performing SVD to the large TCC matrix, making it much more runtime efficient than the conventional SVD method. Furthermore, the grid size of the kernels can be flexibly set to any desired value in aerial image simulations, which is not realizable with the conventional SVD method. The comparison of aerial image intensity errors and edge placement errors calculated by the proposed method and the conventional SVD method has confirmed the validity of the proposed method. An OPC example is also provided to further demonstrate its efficiency.

Optical Proximity Corrections for Digital Micromirror Device-based Maskless Lithography

We propose optical proximity corrections (OPCs) for digital micromirror device (DMD)-based maskless lithography. A pattern writing scheme is analyzed and a theoretical model for obtaining the dose distribution profile and resulting structure is derived. By using simulation based on this model we were able to reduce the edge placement error (EPE) between the design width and the critical dimension (CD) of a fabricated photoresist, which enables improvement of the CD. Moreover, by experiments carried out with the parameter derived from the writing scheme, we minimized the corner-rounding effect by controlling light transmission to the corners of a feature by modulating a DMD.

Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation

As the VLSI technologies scale down to the sub-wavelength lithographic regime, the process parameter variations lead to severe variability of chip performances. Among many process parameter variations, the gate length variation is one of the most important sources of circuit performance variation. This paper proposes a gate layout pattern regularity enhancement method to reduce the systematic variation of the gate critical dimensions (CD). The proposed method performs a decompaction of a cell layout considering the on-pitch constraints and enhances the pattern regularity under given timing constraints using linear programming. We can enhance the regularity under the timing constraint by modifying non-timing-critical patterns using the proposed method. Experimental results show that 73.7% gate layouts of 25 cells in a 90nm technology are placed perfectly on-pitch by the proposed method with 10% allowable delay increase. Experiment on the edge placement error (EPE) estimation shows that the standard deviation of the gate CD EPE distribution is reduced by about 28% compared to that of the original layouts. These results show that the proposed method is effective for reducing the systematic CD variation.

Synthesis of scanning electron microscopy images by high performance computing for the metrology of advanced CMOS processes

Scanning electron microscopy is still the technique of choice for imaging and for in-line measurement of critical dimensions and overlay accuracy in most of the core technology processes. In particular, critical dimension microscopy provides information about design template matching and edge placement errors through links with design having proven beneficial effects on process yield and product reliability. In this paper, the use of high performance computing is demonstrated to simulate linescans and 2D secondary electron images to be used in optical proximity error correction strategies for nanometer scale technologies.

Performance-Based Optical Proximity Correction Methodology

The rapid reduction in critical dimension of integrated circuits has lead to substantial mask data expansion for mask design based on traditional model-based full-chip optical proximity correction (OPC). Conventional EPE-OPC is mainly based on edge placement error (EPE) without consideration of its effect on circuit performance; often resulting in an overcorrected OPC mask with little improvement in circuit performance at the expense of much higher cost. In this paper, a performance-based OPC (PB-OPC) methodology is proposed taking into account both performance and cost. A less complex mask is generated based on the performance matching criteria. The framework exploits the in situ estimated postlithography performance deviation error to drive the customized mask design algorithm. In particular, device PB-OPC (DPB-OPC) was deployed to systematically synthesize both polysilicon and diffusion masks by using mean drive current deviation as the controlled performance index. The proposed approach is validated via detailed simulation using 65-nm foundry libraries and IEEE International Symposium on Circuits and Systems 1985 (ISCAS'85) benchmark circuits. When compared to conventional performance-aware EPE-OPC approach, the proposed DPB-OPC achieved 34% average reduction in mask size and up to 13.5% reduction in mean drive current deviation within reasonable run time.

ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction

In this paper, we present an efficient lithography aware detailed (ELIAD) router to enhance silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first quantitatively show that a pre-OPC litho-metric is highly uncorrelated with a post-OPC metric, which stresses the importance of a post-OPC litho-metric for design-time optimization. We then propose a compact post-OPC litho-metric for a detailed router (DR) based on statistical characterization, where the interferences among predefined litho-prone shapes are captured as a lookup table. Our litho-metric derived from the characterization shows high fidelity to the total edge placement error (EPE) in large scale, compared with Calibre OPC/optical rule check. Therefore, ELIAD powered by the proposed litho-metric can enhance the overall post-OPC printed silicon image. Experimental results on 65-nm industrial circuits show that ELIAD outperforms a rip-up/rerouting approach such as Resolution-enhancement-technique-Aware Detailed Routing with 8times more EPE hot spot reduction and 12times speedup. Moreover, compared with a conventional DR, ELIAD is only about 50% slower.

Auxiliary pattern-based optical proximity correction for better printability, timing, and leakage control

Optical proximity correction OPC is a mandatory resolution enhancement technique RET to ensure the printability of layout fea- tures in silicon. The most prominent OPC method, model-based OPC, alters the layout data for the photomask that enables drawn layout fea- tures to be accurately reproduced by lithography and etch processes onto the wafer. This technique in various forms has now become stan- dard in integrated circuit IC manufacturing at 0.18 m and below. How- ever, model-based OPC is computationally expensive and its runtime increases with technology scaling. The cell-based OPC approach im- proves runtime by performing OPC once per cell definition, as opposed to once per cell instantiation in the layout. However, cell-based OPC does not comprehend intercell optical interactions that affect feature printability in a layout context. This leads to printability, and conse- quently, performance and leakage, degradation. In this work, we propose auxiliary pattern-enabled cell-based OPC to improve printability of cell- based OPC, while retaining its runtime advantage. Auxiliary patterns AP are nonfunctional poly features that are added around a standard cell to shield it from optical proximity effects. We present the AP-based OPC approach and demonstrate its advantages over cell-based and model-based OPC in terms of printability as well as timing and leakage variabilities. AP-based OPC improves the edge placement error over cell-based OPC by 68%. To enable effective insertion of AP in cell in- stances at a full-chip layout level, we propose a dynamic programming DP-based method for perturbation of detailed placement. Our approach modifies the detailed placement to allow opportunistic insertion of AP around cell instances in the design layout. By perturbing placement, we achieve 100% AP applicability in designs with placement utilization less than 70%. AP-based OPC also reduces leakage and timing variability compared to conventional cell-based OPC. We further demonstrate that AP insertion achieves timing and leakage variability comparable to that of model-based OPC. © 2008 Society of Photo-Optical Instrumentation Engineers.

Wire Sizing and Spacing for Lithographic Printability and Timing Optimization

As the VLSI feature size has already decreased below lithographic wavelength, the printability problem, due to strong diffraction effects, poses a serious threat to the progress of VLSI technology. A circuit layout with poor printability implies that it is difficult to make the printed features on wafers follow designed shapes without distortions. The development of resolution enhancement techniques (RET) can alleviate the printability problem but cannot reverse the trend of deterioration. Moreover, over-usage of RET may dramatically increase photo-mask cost and increase the cycle time for volume production. Thus, there is a strong demand to consider the subwavelength printability problem in circuit layout designs. However, layout printability optimization should not degrade circuit timing performance. In this paper, we introduce a wire sizing and spacing method to improve wire printability with minimal adverse impact on interconnect timing performance. A new printability model is proposed to handle partially coherent illuminations. The complex printability and timing optimization problem is solved in a two-phase approach. The difficulty of the printability optimization due to its multimodal nature is handled with a sensitivity-based heuristic. A coupling aware timing driven continuous wire sizing algorithm is also provided. Lithographic simulation results show that our approach can improve the printability in term of edge placement error (EPE) by 20%-40% without violating timing, wire width, and spacing constraints.

True process variation aware optical proximity correction with variational lithography modeling and model calibration

Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional model-based OPC assumes nominal process conditions without considering process variations because of the lack of variational lithography models. A simple method to improve OPC results under process variations is to sample multiple process conditions across the process window, which requires long run times. We derive a variational lithography model (VLIM) that can simulate across the process window without much run-time overhead compared to the conventional lithography models. To match the model to experimental data, we demonstrate a VLIM calibration method. The calibrated model has accuracy comparable to nonvariational models, but has the advantage of taking process variations into consideration. We introduce the variational edge placement error (VEPE) metrics based on the model, a natural extension to the edge placement error (EPE) used in conventional OPC algorithms. A true process-variation aware OPC (PVOPC) framework is proposed used the VEPE metric. Due to the analytical nature of VLIM, our PVOPC is only about 2 to 3× slower than the conventional OPC, but it explicitly considers the two main sources of process variations (exposure dose and focus variations) during OPC. Thus our post-PVOPC results are much more robust than the conventional OPC ones, in terms of both geometric printability and electrical characterization under process variations.

Wafer Topography-Aware Optical Proximity Correction

Depth of focus is the major contributor to lithographic process margin. One of the major causes of focus variation is imperfect planarization of fabrication layers. Presently, optical proximity correction (OPC) methods are oblivious to the predictable nature of focus variation arising from wafer topography. As a result, designers suffer from manufacturing yield loss as well as loss of design quality through unnecessary guardbanding. In this paper, the authors propose a novel flow and method to drive OPC with a topography map of the layout that is generated by chemical-mechanical polishing simulation. The wafer topography variations result in local defocus, which the authors explicitly model in the OPC insertion and verification flows. In addition, a novel topography-aware optical rule check to validate the quality of result of OPC for a given topography is presented. The experimental validation in this paper uses simulation-based experiments with 90-nm foundry libraries and industry-strength OPC and scattering bar recipes. It is found that the proposed topography-aware OPC (TOPC) can yield up to 67% reduction in edge placement errors. TOPC achieves up to 72% reduction in worst case printability with little increase in data volume and OPC runtime. The electrical impact of the proposed TOPC method is investigated. The results show that TOPC can significantly reduce timing uncertainty in addition to process variation

Simulation-Based Automatic Optical Proximity Effect Correction Adaptive for Device Fabrication

A new optical proximity effect correction (OPC) method adaptive for device fabrication has been developed, focusing on the evaluation method of printed images through simulation. The evaluation procedure of this method is consist of not only measurement of edge placement error of the printed image but analysis of the shape of the printed image. Automatic correction which is flexible for various pattern shapes is available, and distortion via overcorrection is prevented. By using this method for 0.28 µ m static random access memory (SRAM) poly-Si patterns, an excellent distortion-free printed image adequate for actual device fabrication processing has been obtained with simple mask patterns. The SRAM cell size was reduced to as small as 5 µ m2.

Dose, shape, and hybrid modifications for PYRAMID in electron beam proximity effect correction

As the dimensions of circuit primitives are reduced, the proximity effect becomes an increasingly important limiting factor in the fabrication of high density integrated circuits using electron beam (e-beam) lithography. In the past, proximity effect correction schemes have in general utilized one of two different approaches: dose or shape modification. Previously, PYRAMID, a hierarchical, rule-based proximity effect correction scheme which has been demonstrated to be able to correct circuit patterns with a minimum feature size of 0.1 μm was successfully presented. Although PYRAMID has been implemented with a pattern shape modification technique, its correction algorithms are not limited to this approach. In this article, the two approaches are compared in details in terms of CD error (edge placement error) and edge contrast, using the two corresponding versions of PYRAMID. A hybrid approach, i.e., combination of dose and shape modifications, is also considered.

Designing Fourier Descriptor-Based Geometric Models for Object Interpretation in Medical Images Using Genetic Algorithms

In previous work we have modeled simple 3D anatomical objects using deformed superquadrics and established their optimal position with the aid of genetic algorithms (GAs). Here we extend the complexity of the search object using 3D Fourier descriptor (FD) representations and allow GAs once again to optimize the object's shape and position. Using magnetic resonance image data, we perform an approximate segmentation on one lateral ventricle in the brain and use the FDs from this as seeding values for the GAs to search for the left and right lateral ventricles in seven 3D data sets. We show that the method is capable of coping with normal biological variation. Finally, we compare FD/GA-guided segmentation with a manually guided interactive region growing method and find an agreement of 78 ± 10% in voxel classification with a corresponding average edge placement error of 2.2 ± 0.4 mm.

An application of genetic algorithms to geometric model-guided interpretation of brain anatomy

This work applies 3D Fourier Descriptors (FDs) and Genetic Algorithms (GAs) to the optimisation of the shape and position of models of anatomical objects within the human brain. Using magnetic resonance image data, we perform an approximate segmentation on one lateral ventricle and use the FDs from this as seeding values for the GAs to search for the left and right lateral ventricles in subsequent 3I) image data sets, showing that the method is capable of coping with normal biological variation within and between individuals. Finally, we compare the GA-guided segmentation with a manual region growing method and find an agreement of 79.9±5.8% in voxel classification with a corresponding mean edge placement error of 2.1±0.4 mm.

Practical Optical Proximity Effect Correction Adopting Process Latitude Consideration

For an optical lithography process with a design rule of under 0.35 µ m, printed resist pattern size and shape tend to differ from those designed because of the optical proximity effect, resulting in line width error and corner rounding. In order to solve such problems, a new optical proximity effect correction (OPC) system taking account of the resist development and process latitude has been developed. The system is designed focussing on accurate optimization of cell patterns such as memory or gate array devices. Using this OPC for a memory device cell pattern of 3.5×6.3 µ m area, the resist edge placement error with process conditions of within ±5% exposure latitude and ±0.75 µ m depth of focus achieved was one-third of that without OPC. The calculation time for this correction is as short as 2 minutes on a 135 MIPS workstation even with the resist development and process latitude consideration.