Dynamic Voltage Frequency Scaling Research Articles

Detection of and Countermeasure Against Thermal Covert Channel in Many-Core Systems

The thermal covert channels (TCCs) in many-core systems can cause detrimental data breaches. In this article, we present a three-step scheme to detect and fight against such TCC attacks. Specifically, in the detection step, each core calculates the spectrum of its own CPU workload traces that are collected over a few fixed time intervals, and then it applies a frequency scanning method to detect if there exists any TCC attack. In the next positioning step, the logical cores running the transmitter threads are located. In the last step, the physical CPU cores suspiciously engaging in a TCC attack have to undertake dynamic voltage frequency scaling (DVFS) such that any possible TCC trace will be essentially wiped out. Our experiments have confirmed that on average 97&#x0025; of the TCC attacks can be detected, and with the proposed defense, the packet error rate (PER) of a TCC attack can soar to more than 70&#x0025;, literally shutting down the attack in practical terms. The performance penalty caused by the inclusion of the proposed DVFS countermeasures is found to be only 3&#x0025; for an <inline-formula> <tex-math notation="LaTeX">$8\times 8$ </tex-math></inline-formula> many-core system.

0–1 ILP-based run-time hierarchical energy optimization for heterogeneous cluster-based multi/many-core systems

Heterogeneous cluster-based multi/many-core platforms are on the edge, delivering high computing and energy-efficient embedded systems. These platforms support Dynamic Voltage/Frequency Scaling (DVFS), allowing to change the voltage/frequency levels for each cluster independently. Mapping dynamic applications on such platforms at run-time is a tedious task. This article presents a 0–1 Integer Linear Programming (ILP) based run-time management approach that aims to optimize the overall system energy. The proposed approach adopts a hierarchical management organization. A global management strategy determines application-to-cluster assignments and setups the cluster frequency configurations. A local management strategy determines task-to-core mapping in each cluster to minimize resource usage. Our approach achieves optimized solutions with reduced complexity and shows good scalability on different platform sizes. The experimental results show that, compared with the state-of-the-art approaches of similar complexity, the proposed global management strategy can reduce the average power consumption of the overall system by 80.3%. The experiment also demonstrates that resource minimization in the local management can significantly impact global management decisions, and thereby further reducing overall average power by up to 60.72%.

Online frequency-based performance and power estimation for clustered multi-processor systems

Modern Chip Multi-Processors (CMPs) are required to be increasingly power efficient while also offering higher performance and lower costs. A combination of Dynamic Voltage–Frequency Scaling (DVFS) and sophisticated resource-aware scheduling is needed to address the underlying problem of maximizing performance-per-Watt of CMP architectures. In this paper, we propose a methodology to predict the power consumption and performance for groups of concurrently executing applications at all available frequencies of a CMP. The methodology uses a combination of hardware-based application profiling, contention-aware scheduling, and artificial neural networks. Experimental results on an Odroid-XU3 board demonstrate an increase in average performance per Watt of 30.5% (A15 cluster) and 11.4% (A7 cluster) over Linux’s Completely Fair Scheduler (CFS) and power governors. In addition, our methodology outperforms three state-of-the-art resource managers, yielding the highest performance per Watt in all evaluated use cases.

Energy-minimized Scheduling of Real-time Parallel Workflows on Heterogeneous Distributed Computing Systems

Today's large-scale parallel workflows are often processed on heterogeneous distributed computing platforms. From an economic perspective, computing resource providers should minimize the cost while offering high service quality. It has become well-recognized that energy consumption accounts for a large part of a computing system's total cost, and timeliness and reliability are two important service indicators. This work studies the problem of scheduling a parallel workflow that minimizes the system energy consumption under the constraints of response time and reliability. We first mathematically formulate this problem as a Non-linear Mixed Integer Programming problem. Since this problem is hard to solve directly, we present some highly-efficient heuristic solutions. Specifically, we first develop an algorithm that minimizes the schedule length while meeting reliability requirement, on top of which we propose a processor-merging algorithm and a slack time reclamation algorithm using a dynamic voltage frequency scaling (DVFS) technique to reduce energy consumption. The processor-merging algorithm tries to turn off some energy-inefficient processors such that energy consumption can be minimized. The DVFS technique is applied to scale down the processor frequency at both processor and task levels to reduce energy consumption. Experimental results on two real-life workflows and extensive synthetic parallel workflows demonstrate their effectiveness.

DTaPO: Dynamic Thermal-Aware Performance Optimization for Dark Silicon Many-Core Systems

Future many-core systems need to handle high power density and chip temperature effectively. Some cores in many-core systems need to be turned off or ‘dark’ to manage chip power and thermal density. This phenomenon is also known as the dark silicon problem. This problem prevents many-core systems from utilizing and gaining improved performance from a large number of processing cores. This paper presents a dynamic thermal-aware performance optimization of dark silicon many-core systems (DTaPO) technique for optimizing dark silicon a many-core system performance under temperature constraint. The proposed technique utilizes both task migration and dynamic voltage frequency scaling (DVFS) for optimizing the performance of a many-core system while keeping system temperature in a safe operating limit. Task migration puts hot cores in low-power states and moves tasks to cooler dark cores to aggressively reduce chip temperature while maintaining high overall system performance. To reduce task migration overhead due to cold start, the source core (i.e., active core) keeps its L2 cache content during the initial migration phase. The destination core (i.e., dark core) can access it to reduce the impact of cold start misses. Moreover, the proposed technique limits tasks migration among cores that share the last level cache (LLC). In the case of major thermal violation and no cooler cores being available, DVFS is used to reduce the hot cores temperature gradually by reducing their frequency. Experimental results for different threshold temperatures show that DTaPO can keep the average system temperature below the thermal limit. Affirmatively, the execution time penalty is reduced by up to 18% compared with using only DVFS for all thermal thresholds. Moreover, the average peak temperature is reduced by up to 10.8°C. In addition, the experimental results show that DTaPO improves the system’s performance by up to 80% compared to optimal sprinting patterns (OSP) and reduces the temperature by up to 13.6°C.

Run‐time neuro‐fuzzy type‐2 controller for power optimisation of GP‐GPU architecture

The increasing demand for high-performance computing has emphasised the invocation of sophisticated multi/many-core computing architecture. Graphical Processing Unit (GPU) is considered to be an essential innovation in this regard as GPU offers a significant amount of parallelism in the execution of complex computing applications. The performance of GPUs in reducing the computational time of such applications is worth mentioning. Although GPUs appear to be a problem-solving solution for complex applications yet high power consumption has been a challenging problem, associated with this many-core computer architecture. Efficient resource management is a emerging and promising solution to this challenge; however, reducing the resources would degrade the system's overall performance. On the other hand, reducing the resources based on the analysis of workload can save significant power without degrading the system's overall performance. Therefore, a smart controller to optimise the resources of general purpose-GPU (GP-GPU) architecture is required. AFBRMC-2, a neuro-fuzzy type-2 based controller, is presented for GP-GPU architecture and, based on a feedback mechanism, keeps analysing the stats of processor and manages resources using dynamic voltage frequency scaling and core gating techniques. The proposed controller achieved up to 55% reduction in power consumption against various benchmarks on the NVIDIA TK1 GPU kit.

Dynamic workload-aware DVFS for multicore systems using machine learning

With growing heterogeneity and complexity in applications, demand to design an energy-efficient and fast computing system in multi-core architecture has heightened. This paper presents a regression-based dynamic voltage frequency scaling model which studies and utilizes workload characteristics to obtain optimal voltage–frequency (v–f) settings. The proposed framework leverages the workload profile information together with power constraints to compute the best-suited voltage–frequency (v–f) settings to (a) maintain global power budget at chip-level, (b) maximize performance while enforcing power constraints at the per-core level. The presented algorithm works in conjunction with the workload characterizer and senses change in application requirements and apply the knowledge to select the next setting for the core. Our results when compared with two state-of-the-art algorithms MaxBIPS and TPEq achieve the average power reduction of 33% and 25% respectively across 32-core architecture for PARSEC benchmarks.

Cooperative mobile edge computing‐cloud computing in Internet of vehicle: Architecture and energy‐efficient workload allocation

AbstractWith the increasing number of vehicles, the generating vehicular data exceeds the capacity of mobile edge computing (MEC). Therefore, studying the interaction and collaboration of edge computing and cloud computing is of significance to provide vehicular users with low‐latency high‐rate services. This paper first proposes a MEC‐cloud computing collaboration architecture for Internet of vehicles, then designs the interconnection/interaction framework between MEC and cloud computing. We consider reducing computation delay and power consumption, and formulate an energy‐efficient workload allocation problem with load balancing and dynamic voltage frequency scaling technology, to obtain the optimal workload allocations of MEC and cloud computing. We then present the overall distribution optimization algorithm to solve this problem. The simulation and numerical results show that by saving communication bandwidth and reducing transmission delay, MEC significantly enhances the performance of cloud computing. Besides, the proposed workload balance scheme is better than the benchmark schemes in terms of power consumption and latency.

RETRACTED ARTICLE: A novel scheduling approach to improve the energy efficiency in cloud computing data centers

Cloud computing is the combination of grid computing, distributed computing and utility computing. Cloud computing provides various types of services (servers and storage facility) in the on demand basis. The main goal of the cloud computing is to preserve and organize the very huge data center or data forms. The data forms are composed of thousands of servers that absorb the giant (ample) amount of electricity in the word of energy. The decreasing the energy consumption in datacenter is the major challenge in cloud computing now a day. This research article is going to address the problem of high energy consumption at datacenter. Concentrate on virtual machine scheduling in cloud datacenter with Dynamic Voltage Frequency Scaling (DVFS) approach. We have combined shortest job first and Round Robin algorithms with Vibrant Quantum. This combination of algorithm is considered as shortest round vibrant queue (SRVQ) algorithm. SRVQ reduces the waiting time of the scheduling process and minimize the starvation. The DVFS and SRVQ worked together and produced fruitful results in the final experiments. This work reduced the server’s energy consumption in the cloud data center. In the final results, our proposed framework exhibits 45% of energy efficiency compare to other previously proposed algorithms. 33% of QoS performance were enhanced by our framework.

Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems

Reducing the energy expended to carry out a computational task is important. In this work, we explore the prospects of meeting Quality-of-Service requirements of tasks on a multi-core system while adjusting resources to expend a minimum of energy. This paper considers, for the first time, a QoS-driven coordinated resource management algorithm (RMA) that dynamically adjusts the size of the per-core last-level cache partitions and the per-core voltage–frequency settings to save energy while respecting QoS requirements of every application in multi-programmed workloads run on multi-core systems. It does so by doing configuration-space exploration across the spectrum of LLC partition sizes and Dynamic Voltage–Frequency Scaling (DVFS) settings at runtime at negligible overhead. We show that the energy of 4-core and 8-core systems can be reduced by up to 18% and 14%, respectively, compared to a baseline with even distribution of cache resources and a fixed mid-range core voltage–frequency setting. The energy savings can potentially reach 29% if the QoS targets are relaxed to 40% longer execution time.

A smart energy and reliability aware scheduling algorithm for workflow execution in DVFS-enabled cloud environment

The energy consumption is one of the major concerns addressed by recent researches in the green cloud environment. As a result, to decrease the enormous increase in energy consumption, one of the most promising scheduling techniques used nowadays is the Dynamic Voltage Frequency Scaling (DVFS) technique. DVFS reduces energy consumption by lowering the processors’ frequency for virtual machines (VMs); this results in an increase in the occurrence of errors during the execution of the workflow, which decreases the reliability of the system. As a consequence, this paper addresses the DVFS problem by proposing a new Smart Energy and Reliability Aware Scheduling algorithm (SERAS) for workflow execution in the cloud environment. The SERAS approach split the target deadline of workflow across tasks. Afterward, the proposed algorithm decreases the frequency of processors for VMs using the DVFS technique without missing the tasks’ deadline. As a consequence, the SERAS algorithm allocates the tasks to the most appropriate VMs with suitable frequencies levels while guaranteeing both the reliability and the completion time requirement of green cloud systems. To vindicate the effectiveness of the SERAS algorithm in real-world applications, we carried out a series of experiments on four real workflows generated using a scientific toolkit. Also, we performed comprehensive experiments with recent researches. The results showed that the SERAS algorithm outperforms its competitors while keeping both the reliability and completion time requirements. Furthermore, the estimated time complexity and average execution time show the applicability of the SERAS algorithm compared with their competitors.

Carbon-Efficient Virtual Machine Placement Based on Dynamic Voltage Frequency Scaling in Geo-Distributed Cloud Data Centers

The tremendous growth of big data analysis and IoT (Internet of Things) has made cloud computing an integral part of society. The prominent problem associated with data centers is the growing energy consumption, which results in environmental pollution. Data centers can reduce their carbon emissions through efficient management of server power consumption for a given workload. Dynamic voltage frequency scaling (DVFS) can be applied to control the operating frequencies of the servers based on the workloads assigned to them, as this approach has a cubic increment relationship with power consumption. This research work proposes two DVFS-enabled host selection algorithms for virtual machine (VM) placement with a cluster selection strategy, namely the carbon and power-efficient optimal frequency (C-PEF) algorithm and the carbon-aware first-fit optimal frequency (C-FFF) algorithm.The main aims of the proposed algorithms are to balance the load among the servers and dynamically tune the cooling load based on the current workload. The cluster selection strategy is based on static and dynamic power usage effectiveness (PUE) values and the carbon footprint rate (CFR). The cluster selection is also extended to non-DVFS host selection policies, namely the carbon- and power-efficient (C-PE) algorithm, carbon-aware first-fit (C-FF) algorithm, and carbon-aware first-fit least-empty (C-FFLE) algorithm. The results show that C-FFF achieves 2% more power reduction than C-PEF and C-PE, and demonstrates itself as a power-efficient algorithm for CO2 reduction, retaining the same quality of service (QoS) as its counterparts with lower computational overheads.

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration settling time, independent of the dynamic range of the load or output capacitor value. Measurement results of a 10-bit PG design demonstrate a droop of 100 mV for 500 mA (2 A/ns $di/dt$ ) with settling times < 20 ns. The CDLDO design is presented with the key equations and timing diagrams to show the operating principle of the concept. Methods to accommodate resiliency to process, voltage and temperature (PVT) and wide dynamic voltage frequency scaling (DVFS) conditions are also discussed in detail.

Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles

Stereo matching is a promising approach for smart vehicles to find the depth of nearby objects. Transforming a traditional stereo matching algorithm to its adaptive version has potential advantages to achieve the maximum quality (depth accuracy) in a best-effort manner. However, it is very challenging to support this adaptive feature, since (1) the internal mechanism of adaptive stereo matching (ASM) has to be accurately modeled, and (2) scheduling ASM tasks on multiprocessors to generate the maximum quality is difficult under strict real-time constraints of smart vehicles. In this article, we propose a framework for constructing an ASM application and optimizing its output quality on smart vehicles. First, we empirically convert stereo matching into ASM by exploiting its inherent characteristics of disparity–cycle correspondence and introduce an exponential quality model that accurately represents the quality–cycle relationship. Second, with the explicit quality model, we propose an efficient quadratic programming-based dynamic voltage/frequency scaling (DVFS) algorithm to decide the optimal operating strategy, which maximizes the output quality under timing, energy, and temperature constraints. Third, we propose two novel methods to efficiently estimate the parameters of the quality model, namely location similarity-based feature point thresholding and street scenario-confined CNN prediction. Results show that our DVFS algorithm achieves at least 1.61 times quality improvement compared to the state-of-the-art techniques, and average parameter estimation for the quality model achieves 96.35% accuracy on the straight road.

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM is implemented in a 1× nm DRAM process. Various techniques are applied to achieve higher bandwidth and lower power than LPDDR4X. To increase data rate, a WCK clocking scheme that is less vulnerable to power noise is adopted and a non-target ODT mode is proposed to reduce reflection noise in a two-rank system. A couple of techniques are proposed for saving power. To reduce self-refresh power, this chip supports deep sleep mode (DSM). In DSM, the leakage current of internal voltages decreases by disabling internal voltage generators that are not related with a self-refresh operation. Dynamic voltage frequency scaling (DVFS) is adopted to reduce read and write operation power and when writing all zeros data, an internal data copy function can be used for reducing write operation power. Last, a ZQ calibration scheme that shares one ZQ resistor (RZQ) and automatically executes ZQ calibration is presented. The proposed LPDDR5 DRAM operates up to 7.5 Gb/s on an automatic test equipment (ATE) and 6.4 Gb/s on a prototype system. Read and write power decrease by 21% and 33% compared to LPDDR4X at 4.266 Gb/s, and self-refresh power is reduced by 25% in DSM.

Multiobjective Optimization of SAR Reconstruction on Hybrid Multicore Systems

Hybrid multicore processors (HMPs) are poised to dominate the landscape of the next generation of computing on the desktop as well as on exascale systems. HMPs consist of general purpose CPU cores along with specialized coprocessors and can provide high performance for a wide spectrum of applications at significantly lower energy requirements per floating-point operations per second (FLOP). In this article, we develop parallel algorithms and software for constructing multiresolution synthetic aperture radar images on HMPs. We develop several load balancing algorithms for optimizing time performance and energy on HMPs. We also present a systematic approach for deriving the energy-time performance tradeoffs on HMPs in the presence of dynamic voltage frequency scaling. Pareto-optimal curves are presented on a system consisting of 24 traditional cores and a GPU.

Performance Profiling of Embedded ConvNets under Thermal-Aware DVFS

Convolutional Neural Networks (ConvNets) can be shrunk to fit embedded CPUs adopted on mobile end-nodes, like smartphones or drones. The deployment onto such devices encompasses several algorithmic level optimizations, e.g., topology restructuring, pruning, and quantization, that reduce the complexity of the network, ensuring less resource usage and hence higher speed. Several studies revealed remarkable performance, paving the way towards real-time inference on low power cores. However, continuous execution at maximum speed is quite unrealistic due to a fast increase of the on-chip temperature. Indeed, proper thermal management is paramount to guarantee silicon reliability and a safe user experience. Power management schemes, like voltage lowering and frequency scaling, are common knobs to control the thermal stability. Obviously, this implies a performance degradation, often not considered during the training and optimization stages. The objective of this work is to present the performance assessment of embedded ConvNets under thermal management. Our study covers the behavior of two control policies, namely reactive and proactive, implemented through the Dynamic Voltage-Frequency Scaling (DVFS) mechanism available on commercial embedded CPUs. As benchmarks, we used four state-of-the-art ConvNets for computer vision flashed into the ARM Cortex-A15 CPU. With the collected results, we aim to show the existing temperature-performance trade-off and give a more realistic analysis of the maximum performance achievable. Moreover, we empirically demonstrate the strict relationship between the on-chip thermal behavior and the hyper-parameters of the ConvNet, revealing optimization margins for a thermal-aware design of neural network layers.

Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling

This article introduces a systematic methodology to design microarchitectures that are reconfigurable down to the pipeline stage. Reconfigurable microarchitectures were showed to provide significant energy improvements in accelerators under wide-voltage scaling. However, prior art is based on ad hoc techniques that limit their applicability, without addressing the challenge of enabling general design flows for reconfigurable microarchitectures. The proposed methodology introduces the unprecedented capability of translating a conventional fixed microarchitecture into a reconfigurable one. The methodology relies on commercial EDA tools, which are integrated into a design flow through the manipulation of the gate-level netlist via a set of graph algorithms. The proposed methodology is shown to be architecture-agnostic, fully automated, and applicable to designs that are either developed at the register transfer level (RTL), or provided by third-party soft IP vendors. Ultimately, the proposed methodology allows to add microarchitectural adjustment as a run-time knob to augment the energy benefits of wide-voltage scaling. Reconfiguration is shown to improve the energy efficiency by up to 35% beyond the conventional dynamic voltage frequency scaling (DVFS), through the analysis of various test vehicles.

An Efficient Fault-Tolerant Scheduling Approach with Energy Minimization for Hard Real-Time Embedded Systems

Abstract In this paper, we focus on two major problems in hard real-time embedded systems fault tolerance and energy minimization. Fault tolerance is achieved via both checkpointing technique and active replication strategy to tolerate multiple transient faults, whereas energy minimization is achieved by adapting Dynamic Voltage Frequency Scaling (DVFS) technique. First, we introduce an original fault-tolerance approach for hard real-time systems on multiprocessor platforms. Based on this approach, we then propose DVFS_FTS algorithm for energy-efficient fault-tolerant scheduling of precedence-constrained applications. DVFS_FTS is based on a list scheduling heuristics, it satisfies real-time constraints and minimizes energy consumption even in the presence of faults by exploring the multiprocessor architecture. Simulation results reveal that the proposed algorithm can save a significant amount of energy while preserving the required fault-tolerance of the system and outperforms other related approaches in energy savings.

Runtime adaptive Dynamic Voltage Frequency Scaling technique for reducing the power consumption in Multi Processor System On Chip

Runtime adaptive Dynamic Voltage Frequency Scaling technique for reducing the power consumption in Multi Processor System On Chip