Dynamic Voltage Frequency Scaling Research Articles

Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence

Technology scaling of complementary metal–oxide–semiconductor has resulted in new thermal behavior where increase in operating temperature results in reduced circuit propagation delay. This paper exploits this inverse thermal dependence (ITD) for power, performance, and temperature optimization in single-core and multicore processor architectures for various thermally hot and cold applications. Since ITD increases the maximum achievable operating frequency of a processor at high temperatures, it is used to reduce the execution time of applications. Dynamic thermal management (DTM) techniques, such as activity migration (AM), dynamic voltage frequency scaling (DVFS), and throttling, are modified to leverage ITD to either enhance the performance or the energy efficiency. While recent work observed the ITD effect for 45- and 32-nm technologies, in this paper, we explore future technologies through predictive SPICE models for 20-, 14-, 10-, and 7-nm technologies. The results show that the ITD-aware techniques reduce the execution time, energy-delay product (EDP) and energy-delay-square product by up to 28%, 33%, and 48%, respectively. Moreover, the ITD-aware DVFS yields the lowest execution time while resulting in the most uniform thermal profile and thus enhanced reliability. Overall, the ITD-aware techniques reduce the execution time and EDP, both in combination with DTM techniques or stand-alone, especially at lower than nominal operating voltages.

A new rule-based power-aware job scheduler for supercomputers

The fast processing speeds of the current generation of supercomputers provide a great convenience to scientists dealing with extremely large data sets. The next generation of exascale supercomputers could provide accurate simulation results for the automobile industry, aerospace industry, and even nuclear fusion reactors for the very first time. However, the energy cost of super-computing is extremely high, with a total electricity bill of 9 million dollars per year. Thus, conserving energy and increasing the energy efficiency of supercomputers have become critical in recent years. Many researchers have studied this problem and are trying to conserve energy by incorporating the dynamic voltage frequency scaling technique into their methods. However, this approach is limited, especially when the workload is high. In this paper, we developed a power-aware job scheduler by applying a rule-based control method and taking into consideration real-world power and speedup profiles to improve power efficiency while adhering to predetermined power constraints. The intensive simulation results showed that our proposed method is able to achieve the maximum utilization of computing resources as compared to baseline scheduling algorithms while keeping the energy cost under the threshold. Moreover, by introducing a power performance factor based on the real-world power and speedup profiles, we are able to increase the power efficiency by up to 75%.

Dynamic frequency scaling for embedded systems with memory intensive applications

Power management of embedded systems is an important issue as they are powered from a limited energy storage. To reduce the power consumption of the processor, dynamic frequency/voltage scaling (DFS) technique has been used widely in embedded systems. In this paper, we consider the cycles per instruction (CPI) as the primary indicator of energy efficiency. On a real target hardware, we observe that memory access affects the CPI, and found that the high CPI lowers the energy efficiency and the performance gain by frequency scaling. With this observation, a new DFS algorithm based on the CPI is proposed. Experimental results show the proposed DFS algorithm provides higher energy efficiency for memory-intensive application; it reduces the energy consumption by 28.6%, without causing delay in execution. The proposed algorithm is mainly designed for memory-intensive applications, but it works well with CPU-intensive applications and mixed type of applications also.

LACE: A Locust-Inspired Scheduling Algorithm to Reduce Energy Consumption in Cloud Datacenters

The growth of cloud computing has resulted in uneconomic energy consumption, which has negatively impacted the environment through the generation of carbon emissions. This paper proposes a distributed Locust-inspired scheduling algorithm to reduce cloud computing consumed energy (LACE). LACE schedules and optimizes the allocation of virtual machines (VMs) based on behavior derived from locusts. LACE distributes scheduling among servers; each server is responsible for allocating and migrating its VMs. Hence, the scheduling load is distributed between servers rather than being centralized in one component. LACE was thoroughly evaluated by comparing it with long-standing VM scheduling algorithms: dynamic voltage–frequency scaling (DVFS), energy-aware scheduling using the workload-aware consolidation technique, and the static threshold with minimum utilization policy. The experimental results show that LACE considerably outperforms the other algorithms in almost every area. Most importantly, LACE exhibited significant levels of fault tolerance under heavy workloads that benchmarks were unable to sustain.

Energy-Efficient Fault-Tolerant Mapping and Scheduling on Heterogeneous Multiprocessor Real-Time Systems

Energy saving and system reliability are two crucial issues for designing modern multiprocessor systems. There has been reliability-aware power management with dynamic voltage–frequency scaling (DVFS) schemes in recent studies. However, they are limited to optimization under the impact of DVFS on energy and reliability and have not considered reducing the non-negligible leakage energy consumption. In this paper, we focus on co-management of system reliability and total energy for applications with precedence constrained tasks on heterogeneous multiprocessor real-time systems. We first investigate the impact of energy management techniques on both reliability and energy of the systems using task recovery for fault tolerance and then propose an Energy-efficient Fault-tolerant Scheduling (EFS) scheme integrated with power mode management, which can mitigate the negative impact of DVFS on system reliability. To obtain the optimal energy-efficient reliability-guaranteed scheduling for pre-mapped applications on systems considering various realistic issues, we build mixed integer linear programing formulations with the proposed EFS scheme. To address mapping and scheduling for energy-efficiency and fault-tolerance, we finally develop a framework implemented by a List-based Binary Particle Swarm Optimization algorithm. The extensive comparative evaluations for synthetic and realistic benchmarks show that our approaches outperform several related studies in terms of energy consumption and system reliability.

On-line Optimization of Power Efficiency in 3D Multicore Processors

This paper considers the problem of maximizing power efficiency in multi-core processors by dynamic voltage frequency scaling. We formulate the problem in an on-line setting and apply to it a gradient-based stochastic approximation algorithm. We use a cycle-level, full-system simulation platform capable of realistic modeling of state-of-the-art microarchitectures executing industry-standard benchmarks (Splash 2). The optimization algorithm computes the gradients by the Infinitesimal Perturbation Analysis (IPA) sample-based sensitivity analysis technique. Despite the fact that the system’s characteristics vary widely with time and hence the optimum point varies as well, the simulation experiments exhibit a tracking of the optimal values. To our knowledge this is the first application of IPA to co-optimizing throughput performance and power in computer processors.

Dynamic frequency scaling for embedded systems with memory intensive applications

Power management of embedded systems is an important issue as they are powered from a limited energy storage. To reduce the power consumption of the processor, dynamic frequency/voltage scaling (DFS) technique has been used widely in embedded systems. In this paper, we consider the cycles per instruction (CPI) as the primary indicator of energy efficiency. On a real target hardware, we observe that memory access affects the CPI, and found that the high CPI lowers the energy efficiency and the performance gain by frequency scaling. With this observation, a new DFS algorithm based on the CPI is proposed. Experimental results show the proposed DFS algorithm provides higher energy efficiency for memory-intensive application; it reduces the energy consumption by 28.6%, without causing delay in execution. The proposed algorithm is mainly designed for memory-intensive applications, but it works well with CPU-intensive applications and mixed type of applications also.

A power saver scheduling algorithm using DVFS and DNS techniques in cloud computing data centres

Cloud computing is a fascinating and profitable area in modern distributed computing. Aside from providing millions of users the means to use offered services through their own computers, terminals, and mobile devices, cloud computing presents an environment with low cost, simple user interface, and low power consumption by employing server virtualisation in its offered services (e.g., Infrastructure as a Service). The pool of virtual machines found in a cloud computing data centre (DC) must run through an efficient task scheduling algorithm to achieve resource utilisation and good quality of service, thus ensuring the positive effect of low energy consumption in the cloud computing environment. In this paper, we present an energy-efficient scheduling algorithm for a cloud computing DC using the dynamic voltage frequency scaling technique. The proposed scheduling algorithm can efficiently reduce the energy consumption for executing jobs by increasing resource utilisation. GreenCloud simulator is used to simulate our algorithm. Experimental results show that, compared with other algorithms, our algorithm can increase server utilisation, reduce energy consumption, and reduce execution time.

A power saver scheduling algorithm using DVFS and DNS techniques in cloud computing data centres

Cloud computing is a fascinating and profitable area in modern distributed computing. Aside from providing millions of users the means to use offered services through their own computers, terminals, and mobile devices, cloud computing presents an environment with low cost, simple user interface, and low power consumption by employing server virtualisation in its offered services (e.g., Infrastructure as a Service). The pool of virtual machines found in a cloud computing data centre (DC) must run through an efficient task scheduling algorithm to achieve resource utilisation and good quality of service, thus ensuring the positive effect of low energy consumption in the cloud computing environment. In this paper, we present an energy-efficient scheduling algorithm for a cloud computing DC using the dynamic voltage frequency scaling technique. The proposed scheduling algorithm can efficiently reduce the energy consumption for executing jobs by increasing resource utilisation. GreenCloud simulator is used to simulate our algorithm. Experimental results show that, compared with other algorithms, our algorithm can increase server utilisation, reduce energy consumption, and reduce execution time.

Synergistic CPU-GPU Frequency Capping for Energy-Efficient Mobile Games

Mobile platforms are increasingly using Heterogeneous Multiprocessor Systems-on-Chip (HMPSoCs) with differentiated processing cores and GPUs to achieve high performance for graphics-intensive applications such as mobile games. Traditionally, separate CPU and GPU governors are deployed in order to achieve energy efficiency through Dynamic Voltage Frequency Scaling (DVFS) but miss opportunities for further energy savings through coordinated system-level application of DVFS. We present a cooperative CPU-GPU DVFS strategy (called Co-Cap) that orchestrates energy-efficient CPU and GPU DVFS through synergistic CPU and GPU frequency capping to avoid frequency overprovisioning while maintaining desired performance. Unlike traditional approaches that target a narrow set of mobile games, our Co-Cap approach is applicable across a wide range of microbenchmarks and mobile games. Our methodology employs a systematic training phase using fine-grained refinement steps with evaluations of frequency capping tables followed by a deployment phase, allowing deployment across a wide range of microbenchmarks and mobile games with varying graphics workloads. Our experimental results across multiple sets of over 200 microbenchmarks and 40 mobile games show that Co-Cap improves energy per frame by on average 8.9% (up to 18.3%) and 7.8% (up to 27.6%) (16.6% and 15.7% in CPU-dominant applications) and achieves minimal frames-per-second (FPS) loss by 0.9% and 0.85% (1.3% and 1.5% in CPU-dominant applications) on average in training and deployment sets, respectively, compared to the default CPU and GPU governors, with negligible overhead in execution time and power consumption on the ODROID-XU3 platform.

Exploiting Approximate MLC-PCM in Low-Power Embedded Systems

Multi-level cell phase change memory (MLC-PCM), because of its very low leakage power and high density, is promising for embedded systems. Furthermore, for applications with inherent low sensitivity to errors, approximate write operations can be exploited in MLC-PCM to improve endurance and performance. However, data that reside in the approximate MLC-PCM for a rather long time without refreshing are prone to soft errors due to resistance drift phenomenon, while even for an application with inherent low sensitivity to errors, a high soft error rate can degrade its Quality of Result (QoR). The architecture-level approaches to decrease the drift effect incur considerable power overhead (about 100%), which is a prominent issue in embedded systems, and are dependent on the number of logic levels stored in the PCM cell (e.g., most of them are designed for 4LC-PCM). This article, taking a different approach, proposes a drift-aware frequency and voltage management to alleviate the drift-based soft-error rate. To this end, first we characterize the application data based on the degree of being exposed to the drift to identify the drift-prone application data. Then we assign the execution frequency and voltage to different regions of the application considering the drift. This frequency assignment speeds up the application regions wherein the drift-prone data are accessed to shorten the lifetime of the drift-prone data, thereby decreasing the soft error rate. An integer linear programming model implements our proposed Dynamic Voltage Frequency Scaling (DVFS). Also, the proposed approach is independent of the number of levels of PCM cells and can be applied to any MLC-PCM system. To evaluate the approach, the approximate MLC-PCM is simulated using empirical models and is integrated into a full-system simulator as data memory. The experimental results show that, by exploiting the approach, QoR is in the acceptable range, while its power overhead is about 84% (on average) less than that of the architecture-level approach.

Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications

In this paper, we present an accuracy-aware operating voltage management unit to improve the lifetime of processors by considering the error-resilient nature of some applications. This unit is placed in the power management unit of the processor and its operation is based on the aggressive operating voltage reduction during the runtime of error resilient applications. This unit determines the operating voltage of the processor based on the type of the running application, the predefined minimum acceptable quality, and the operating voltage level specified by the dynamic voltage frequency scaling controller of the processor power management unit. The determined operating voltage by this unit results in lifetime improvement and power reduction at the cost of timing violations that are tolerable by error-resilient applications. In addition, the proposed unit dynamically adjusts the minimum acceptable operating voltage based on the impact of aging mechanisms. The aging mechanisms considered in this work include Negative Bias Temperature Instability, Hot Carrier Injection, Time Dependent Dielectric Breakdown, Thermal Cycling, Electro-Migration, and Stress Migration. The efficacy of the proposed operating voltage management is investigated by applying it to some exact and error-resilient applications. The results show that the proposed unit lead to, on average, 38.82% lifetime improvement as well as 41.8% power consumption reduction.

DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes

Solar-powered sensor nodes (SCSNs) with energy storages have the greatest potential and are widely used in the coming era of the Internet of Things, since they avoid tedious battery maintenance tasks. However, because the solar energy source is unstable and limited, the sensor nodes suffer from high deadline miss ratio (DMR). To achieve better DMR, the existing scheduling algorithms find the best scheduling scheme in a single period of the recurring task queue and, hence, ignore the long-term performance. To tackle this challenge, this paper proposes a three-level dynamic voltage–frequency scaling (DVFS)-based scheduling strategy to minimize long-term DMR for dual-channel SCSNs. This approach includes a day-level scheduler to achieve a coarse-grained task arrangement, two artificial neural networks to determine the task priorities, and a DVFS-based task selection algorithm for slot-level execution. Experiments show that the proposed scheduler reduces DMR by over 30% on average.

Multi-objective Task Scheduling to Minimize Energy Consumption and Makespan of Cloud Computing Using NSGA-II

The utilization of cloud services has significantly increased due to the easiness in accessibility, better performance, and decrease in the high initial cost. In general, cloud users anticipate completing their tasks without any delay, whereas cloud providers yearn for reducing the energy cost, which is one of the major costs in the cloud service environment. However, reducing energy consumption increases the makespan and leads to customer dissatisfaction. So, it is essential to obtain a set of non-domination solutions for these multiple and conflicting objectives (makespan and energy consumption). In order to control the energy consumption efficaciously, the Dynamic Voltage Frequency Scaling system is incorporated in the optimization procedure and a set of non-domination solutions are obtained using Non-dominated Sorting Genetic Algorithm (NSGA-II). Further, the Artificial Neural Network (ANN), which is one of the most successful machine learning algorithms, is used to predict the virtual machines based on the characteristics of tasks and features of the resources. The optimum solutions obtained using the optimization process with the support of ANN and without the support of ANN are presented and discussed.

Dynamic voltage frequency scaling‐aware refresh management for 3D DRAM over processor architecture

Three-dimensional integrated systems that combine large-capacity dynamic random access memory (DRAM) with high-performance processors represent a promising solution to implementing high-performance computing. However, in such configurations stacked DRAM cells will inevitably be exposed to high temperatures generated by the processor, thereby necessitating DRAMs with high refresh rates driven by embedded temperature sensors. In this Letter, a thermally aware refresh-control method that accounts for abrupt changes in temperature and thermal distribution using low-power techniques such as dynamic voltage frequency scaling is proposed. Comparisons with previous systems via single- and eight-core simulations reveal that the proposed method improves efficiency with no additional overhead.

PoweRock: Power Modeling and Flexible Dynamic Power Management for Many-Core Architectures

Energy-efficient design for green high-performance computing (HPC) is a formidable mission for today's computer scientists. Dynamic power management (DPM) is a key enabling technology involved. While DPM can have various goals for different application scenarios (e.g., enforcing an upper bound on power consumption or optimizing energy usage under a performance-loss constraint), existing DPM solutions are generally designed to meet only one goal and not adaptable to changes in optimization objectives. This paper proposes a novel flexible DPM approach based on a profile-guided dynamic voltage/frequency scaling (DVFS) scheme to meet the different goals. Our contributions include 1) an accurate power prediction model for many-core architectures; 2) a new profiling method for (distributed) shared-memory parallel applications to flexibly determine the optimal frequency and voltage for different phases of the execution; and 3) a hierarchical domain-aware power control design boosting the DPM system scalability for many-core chips. We implement the approach into a working library dubbed PoweRock and evaluate it on the Intel SCC port of the Barrelfish operating system. Experimental results obtained from several well-known benchmarks show that PoweRock attains significant energy and energy-delay product (EDP) improvements (average: 37.1% and 25.5%; best case: 64.0% and 65.4%, respectively) over a static power scheme.

NUTS scheduling approach for cloud data centers to optimize energy consumption

The cloud data center is accommodated with many servers for cloud-based services which cause more consumption of energy and menace cost factors in computing tasks. Many existing scheduling techniques hinge on allocating task where scheduling algorithm is not based on assigning tasks through urgent and non-urgent task scheduling using dynamic voltage frequency scaling (DVFS) controller. In demand to reduce energy consumption and to maintain the quality of services, this paper proposes non-urgent and urgent task scheduling (NUTS) algorithm using DVFS, to restraint and scheduling of task in the more efficient way for minimizing the power consumption of the IT equipment. To increase the energy efficiency, we proposed scheduling queue and non-completed task queue for scheduling urgent, non-urgent and non-completed tasks to ally utilization of resources efficiently and to decrease the consumption of energy in the data center. In this paper, we compared proposed algorithm with two existing standard scheduling algorithms. The experimental results boast that NUTS algorithm performs better than the existing algorithms and can centrist energy efficiency in cloud data center.

A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements

We propose a cache architecture using a 7T/14T SRAM (Fujiwara et al. , 2009) and a control mechanism for reliability enhancements. Our control mechanism differs from conventional dynamic voltage-frequency scaling (DVFS) methods in that it considers not only the cycles per instruction behaviors but also the cache utilization. To measure cache utilization, a novel metric is proposed. The experimental results show that our proposed method achieves 1000 times less bit-error occurrences compared with conventional DVFS methods under the ultralow-voltage operation. Moreover, the results indicate that our proposed method surprisingly not only incurs no performance and energy overheads but also achieves on average a 2.10% performance improvement and a 6.66% energy reduction compared with conventional DVFS methods.

A Power-Scalable Three-Dimensional Streaming Playback Mechanism on Heterogeneous System Architectures

In today’s world, mobile device technologies are advancing with each passing day. People use them to watch videos and deal with important business anywhere. Furthermore, the vigorous development of 3-D streaming technology makes possible the 3-D video conferencing, live broadcast, and online gaming, which made people feel like they were standing right in the scene themselves. However, higher qualities of multimedia streaming are demanded more and more, which necessitates that the content decoding capability of handheld devices be also relatively improved. This is the reason why some handheld devices can execute parallel processing and accelerate decoding processing with extra processes, such as central processing unit, digital signal processor, and graphics processing unit. However, power limitation is one of the inherent restrictions to handheld devices that makes providing high efficiency and energy-saving multimedia streaming service an urgent and interesting challenge. Therefore, a power-scalable 3-D streaming playback mechanism is proposed for the heterogeneous system architecture that is able to adjust the processor frequency or voltage to 3-D streaming service dynamically. In this paper, an immediate and accurate dynamic voltage–frequency scaling prediction mechanism with the properties of dependence for 3-D multimedia streaming decoding features is proposed for power-scalable 3-D streaming playback.

Energy model derivation for the DVFS automatic tuning plugin: tuning energy and power related tuning objectives

Energy consumption will become one of the dominant cost factors that will govern the next generation of large HPC centers. In this paper we present the Dynamic Voltage Frequency Scaling (DVFS) Plugin to automatically tune several energy related tuning objectives at a region-level of HPC applications. This plugin works with the Periscope Tuning Framework which provides an automatic tuning framework including analysis, experiment creation, and evaluation. The tuning actions are based on changes in the frequency via the DVFS. The tuning objectives include the tuning of energy consumption, total cost of ownership, energy delay product and power capping. The tuning is based on a model that relies on performance data and predicts energy consumption, time, and power consumption at different CPU frequencies. The derivation of the models for the DVFS plugin with the principal component analysis is included.