Dynamic Voltage And Frequency Scaling Research Articles

Ring-DVFS: Reliability-Aware Reinforcement Learning-Based DVFS for Real-Time Embedded Systems

Dynamic voltage and frequency scaling (DVFS) is one of the most popular and exploited techniques to reduce power consumption in multicore embedded systems. However, this technique might lead to a task-reliability degradation because scaling the voltage and frequency increases the fault rate and the worst-case execution time of the tasks. In order to preserve task-reliability at an acceptable level as well as achieving power saving, in this letter, we have proposed an enhanced DVFS method based on reinforcement learning to reduce the power consumption of sporadic tasks at runtime in multicore embedded systems without task-reliability degradation. The reinforcement learner takes decisions based on the power savings and task-reliability variations due to DVFS and considers the suitable voltage-frequency level for all tasks such that the timing constraints are met. Experimental evaluation was done on different configurations and with different numbers of tasks to investigate the efficiency of the proposed method. Our experiments show that our proposed method works efficiently than other existing works for reducing power consumption without reliability degradation and deadline misses.

Load balancing in the internet of things using fuzzy logic and shark smell optimization algorithm

PurposeBased on the positive features of the shark smell optimization (SSO) algorithm, the purpose of this paper is to propose a method based on this algorithm, dynamic voltage and frequency scaling (DVFS) model and fuzzy logic to minimize the energy consumption of integrated circuits of internet of things (IoT) nodes and maximize the load-balancing among them.Design/methodology/approachLoad balancing is a key problem in any distributed environment such as cloud and IoT. It is useful when a few nodes are overloaded, a few are under-loaded and the remainders are idle without interrupting the functioning. As this problem is known as an NP-hard one and SSO is a powerful meta-hybrid method that inspires shark hunting behavior and their skill to detect and feel the smell of the bait even from far away, in this research, this study have provided a new method to solve this problem using the SSO algorithm. Also, the study have synthesized the fuzzy logic to counterbalance the load distribution. Furthermore, DVFS, as a powerful energy management method, is used to reduce the energy consumption of integrated circuits of IoT nodes such as processor and circuit bus by reducing the frequency.FindingsThe outcomes of the simulation have indicated that the proposed method has outperformed the hybrid ant colony optimization – particle swarm optimization and PSO regarding energy consumption. Similarly, it has enhanced the load balance better than the moth flame optimization approach and task execution node assignment algorithm.Research limitations/implicationsThere are many aspects and features of IoT load-balancing that are beyond the scope of this paper. Also, given that the environment was considered static, future research can be in a dynamic environment.Practical implicationsThe introduced method is useful for improving the performance of IoT-based applications. We can use these systems to jointly and collaboratively check, handle and control the networks in real-time. Also, the platform can be applied to monitor and control various IoT applications in manufacturing environments such as transportation systems, automated work cells, storage systems and logistics.Originality/valueThis study have proposed a novel load balancing technique for decreasing energy consumption using the SSO algorithm and fuzzy logic.

Intra- and Inter-Server Smart Task Scheduling for Profit and Energy Optimization of HPC Data Centers

Servers in a data center are underutilized due to over-provisioning, which contributes heavily toward the high-power consumption of the data centers. Recent research in optimizing the energy consumption of High Performance Computing (HPC) data centers mostly focuses on consolidation of Virtual Machines (VMs) and using dynamic voltage and frequency scaling (DVFS). These approaches are inherently hardware-based, are frequently unique to individual systems, and often use simulation due to lack of access to HPC data centers. Other approaches require profiling information on the jobs in the HPC system to be available before run-time. In this paper, we propose a reinforcement learning based approach, which jointly optimizes profit and energy in the allocation of jobs to available resources, without the need for such prior information. The approach is implemented in a software scheduler used to allocate real applications from the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark suite to a number of hardware nodes realized with Odroid-XU3 boards. Experiments show that the proposed approach increases the profit earned by 40% while simultaneously reducing energy consumption by 20% when compared to a heuristic-based approach. We also present a network-aware server consolidation algorithm called Bandwidth-Constrained Consolidation (BCC), for HPC data centers which can address the under-utilization problem of the servers. Our experiments show that the BCC consolidation technique can reduce the power consumption of a data center by up-to 37%.

Energy Optimization of Mixed-Criticality Distributed Real-Time Embedded Systems

In this paper, we propose a system-level optimization approach for mixed-criticality distributed real-time systems with safety and energy considerations. We firstly depict a mixed-criticality distributed task model for real-time applications, in which the safety of the system is influenced by dynamic voltage and frequency scaling (DVFS). Due to the huge complexity of solving the problem optimally, a heuristic algorithm is proposed to approach the system-level optimization through a quasi-static scheduling strategy. The experiments demonstrate the efficiency of the proposed approach, which can obtain energy consumption while guaranteeing the system safety requirements.

Extending Performance-Energy Trade-offs Via Dynamic Core Scaling

Modern processors often need to switch among different power states based on usage scenarios, energy availability, and thermal conditions. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management strategy to trade off performance and energy. As transistor scaling is reaching its limit, the viable supply voltage range where DVFS can operate is shrinking, which limits its effectiveness. To extend the performance-energy trade-off capabilities in modern processors, this article proposes dynamic core scaling (DCS) that does not rely on voltage scaling. DCS dynamically adjusts the active superscalar datapath resources so that programs run at a given percentage of their maximum speed while minimizing energy consumption at the same time. Since DCS does not need voltage scaling, it can be combined with DVFS to achieve greater energy savings. To effectively manage performance-energy trade-offs using a combination of DCS and DVFS, this article proposes an oracle controller that demonstrates the optimal control strategy, and two practical controllers that are applicable in real implementations. Evaluations using an 8-way superscalar processor implemented in a 45-nm circuit show that DCS is more effective in performance-energy trade-offs than DVFS at the high performance end for a number of SPEC CPU2000 benchmarks. When used together with DVFS, DCS saves an additional 20 percent of a full-size core’s energy on average. At the minimum operating voltage, DVFS hits its limit, while DCS is still able to achieve an average of 46 percent further energy reduction.

Optimizing Energy in Non-Preemptive Mixed-Criticality Scheduling by Exploiting Probabilistic Information

The strict requirements on the timing correctness biased the modeling and analysis of real-time systems toward the worst-case performances. Such focus on the worst-case, however, does not provide enough information to effectively steer the resource/energy optimization. In this article, we integrate a probabilistic-based energy prediction strategy with the precise scheduling of mixed-criticality tasks, where the timing correctness must be met for all tasks at all scenarios. The dynamic voltage and frequency scaling (DVFS) is applied to this precise scheduling policy to enable energy minimization. We propose a probabilistic technique to derive an energy-efficient speed (for the processor) that minimizes the average energy consumption, while guaranteeing the (worst-case) timing correctness for all tasks, including LO-criticality ones, under any execution condition. We present a response time analysis for such systems under the nonpreemptive fixed-priority scheduling policy. Finally, we conduct an extensive simulation campaign based on randomly generated task sets to verify the effectiveness of our algorithm (with respect to energy savings) and it reports up to 46% energy-saving.

An energy optimization with improved QOS approach for adaptive cloud resources

In recent times, the utilization of cloud computing VMs is extremely enhanced in our day-to-day life due to the ample utilization of digital applications, network appliances, portable gadgets, and information devices etc. In this cloud computing VMs numerous different schemes can be implemented like multimedia-signal-processing-methods. Thus, efficient performance of these cloud-computing VMs becomes an obligatory constraint, precisely for these multimedia-signal-processing-methods. However, large amount of energy consumption and reduction in efficiency of these cloud-computing VMs are the key issues faced by different cloud computing organizations. Therefore, here, we have introduced a dynamic voltage and frequency scaling (DVFS) based adaptive cloud resource re-configurability (ACRR) technique for cloud computing devices, which efficiently reduces energy consumption, as well as perform operations in very less time. We have demonstrated an efficient resource allocation and utilization technique to optimize by reducing different costs of the model. We have also demonstrated efficient energy optimization techniques by reducing task loads. Our experimental outcomes shows the superiority of our proposed model ACRR in terms of average run time, power consumption and average power required than any other state-of-art techniques.

VoltJockey

Based on the concept of hardware separation, ARM introduced TrustZone to build a trusted execution environment for applications. It has been quite successful in defending against various software attacks and forcing attackers to explore vulnerabilities in interface designs and side channels. In this article, we propose an innovative software-controlled hardware fault-based attack, VoltJockey, on multi-core processors that adopt dynamic voltage and frequency scaling (DVFS) techniques for energy efficiency. We deliberately manipulate the processor voltage via DVFS to induce hardware faults into the victim cores, and therefore breaking TrustZone. The entire attack process is based on software without any involvement of hardware, which makes VoltJockey stealthy and hard to prevent.

VoltJockey: A New Dynamic Voltage Scaling-Based Fault Injection Attack on Intel SGX

Intel software guard extensions (SGX) increase the security of applications by enabling them to be performed in a highly trusted space (called enclave). Most state-of-the-art attacks on SGX focus on either mining the software vulnerabilities in the enclave or speculating the secret data with side channels. In this study, we report our recent work on breaking SGX by inducing voltage-oriented hardware faults. The novelty and importance of this attack are that it is completely controlled by software and does not require any security vulnerability in the software. Our proposed attack, called VoltJockey, exploits a vulnerability in the implementation of dynamic voltage and frequency scaling (DVFS) that achieves energy saving by dynamically adjusting the processor's operating voltage and thus clock frequency. However, if the operating voltage is lower than a certain critical level, the circuit's timing constraint will fail and hardware fault would be created. We propose to deliberately trigger such voltage-oriented hardware faults by a loadable kernel module that can set the processor's voltage through Intel's undocumented model-specific register (MSR). We first utilize the module to furnish the processor with a transient low voltage with controlled timing to inject a temporal fault into the target location of the program running in the enclave. Then, we perform a differential fault attack on the outputs before and after the injection of faults. For demonstration, we successfully deploy the proposed attack to extract the key of an AES executed in the enclave and lead an SGX-protected RSA to output our specified result.

An Adaptive CPU-GPU Governing Framework for Mobile Games on big.LITTLE Architectures

Games have been one of the most popular applications on smartphones. In order to meet the increasing computational complexity of mobile games, smartphones are now equipped with heterogeneous CPU multi-core architectures like big.LITTLE as well as high-performance GPUs. However, the integrated CPUs and GPUs drain the battery quickly, which has become a bottleneck for improving user experience. In addition to traditional Dynamic Voltage and Frequency Scaling (DVFS) technique for CPUs and GPUs power reduction, heterogeneous multi-core processors, such as the big.LITTLE architecture, have been designed to offer more opportunity for performance-energy tradeoffs. But current processor governors in smartphones can not exploit these power-saving mechanisms wisely, causing considerable energy waste. In this article, we propose a CPU-GPU governing framework that recognizes the performance demand for different game scenes, and select the most energy-efficient hardware configuration for the corresponding scenes. We implement our framework on an ODROID-XU4 mobile platform, and the experiments show that our framework can achieve 26.7, 16.6, and 10.5 percent power saving on average without compromising user experience when compared to the default governor used in our platform and two governors proposed by other researchers, respectively.

Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design

A number of techniques to achieve power-efficient Network-on-Chips (NoCs) have been proposed, two of which are power-gating and dynamic voltage and frequency scaling (DVFS). Power-gating reduces static power, and DVFS reduces dynamic power. With the goal of reducing both static and dynamic power, it is intuitive to simultaneously deploy both techniques. However, we observe that the straightforward combination of power-gating and DVFS can result in reduced power benefits and degraded performance. In this article, we uniquely combine power-gating and DVFS with the aim of maximizing the NoC power savings and improving performance. The proposed NoC design, called Agile, consists of several architectural designs and a reinforcement learning (RL) based control policy to mitigate the negative effects induced by the combined power-gating and DVFS. Specifically, a simple bypass switch is deployed to maintain network connectivity, avoiding frequently waking up the powered-off router. An optimized pipeline can simplify pipeline stages of the bypass switch to reduce network latency. Reversible link channel buffers can be dynamically allocated to where they are needed to improve throughput. In addition, the RL control policy predicts NoC traffic and decides optimal power-gating decisions, voltage/frequency levels and NoC architecture configurations at runtime. Furthermore, we explore the use of an artificial neural network (ANN) to efficiently reduce the area overhead of implementing RL. We evaluate our design using the PARSEC benchmarks suite. The full system simulation results show that the proposed design improves the overall power savings by up to 58 percent while improving the performance up to 11 percent as compared to state-of-the-art designs. The ANN-based RL implementation and bypass switch incur nominal area overhead of 5 percent, as compared to a conventional router.

PCVM.ARIMA: predictive consolidation of virtual machines applying ARIMA method

Cloud computing adopts virtualization technology, including migration and consolidation of virtual machines, to overcome resource utilization problems and minimize energy consumption. Most of the approaches have focused on minimizing the number of physical machines and rarely have devoted attention to minimizing the number of migrations. They also decide based on the current resources utilization without considering the demand for resources in the future. Some approaches minimize the number of active physical machines and Service Level Agreement (SLA) violations with the number of unnecessary migrations. They consider the current resource utilization of physical machines and neglect from demands for future resource requirements. As a result, as time passes, the number of unnecessary migrations, and subsequently, the rate of SLA violations in data centers increases. Alternatively, several approaches only focus on a hardware level and reduce the physical machine’s dynamic power consumption. The lack of control over the overload of physical machines increases the amount of violation. In this paper, a framework called PCVM.ARIMA is presented that focuses on the dynamic consolidation of virtual machines over the minimum number of physical machines, minimize the number of unnecessary migrations, detect the physical machine overloading, and SLA based on the ARIMA prediction model. Moreover, the Dynamic Voltage and Frequency Scaling (DVFS) technique is used to apply the optimal frequency to heterogeneous physical machines. The experimental results show that the presented framework significantly reduces energy consumption while it improves the QoS factors in comparison to some baseline methods.

Balancing Power And Performance In HPC Clouds

AbstractWith energy consumption in high-performance computing clouds growing rapidly, energy saving has become an important topic. Virtualization provides opportunities to save energy by enabling one physical machine (PM) to host multiple virtual machines (VMs). Dynamic voltage and frequency scaling (DVFS) is another technology to reduce energy consumption. However, in heterogeneous cloud environments where DVFS may be applied at the chip level or the core level, it is a great challenge to combine these two technologies efficiently. On per-core DVFS servers, cloud managers should carefully determine VM placements to minimize performance interference. On full-chip DVFS servers, cloud managers further face the choice of whether to combine VMs with different characteristics to reduce performance interference or to combine VMs with similar characteristics to take better advantage of DVFS. This paper presents a novel mechanism combining a VM placement algorithm and a frequency scaling method. We formulate this VM placement problem as an integer programming (IP) to find appropriate placement configurations, and we utilize support vector machines to select suitable frequencies. We conduct detailed experiments and simulations, showing that our scheme effectively reduces energy consumption with modest impact on performance. Particularly, the total energy delay product is reduced by up to 60%.

Energy-efficient Workload Allocation and Computation Resource Configuration in Distributed Cloud/Edge Computing Systems With Stochastic Workloads

Energy efficiency is one of the most important concerns in cloud/edge computing systems. A major benefit of the Dynamic Voltage and Frequency Scaling (DVFS) technique is that a Virtual Machine (VM) can dynamically scale its computation frequency on an on-demand basis, which is helpful in reducing the energy cost of computation when dealing with stochastic workloads. In this paper, we study the joint workload allocation and computation resource configuration problem in distributed cloud/edge computing. We propose a new energy consumption model that considers the stochastic workloads for computation capacity reconfiguration-enabled VMs. We define Service Risk Probability (SRP) as the probability a VM fails to process the incoming workloads in the current time slot, and we study the energy-SRP tradeoff problem in single VM. Without specifying any distribution of the workloads, we prove that, theoretically there exists an optimal SRP that achieves minimal energy cost, and we derive the closed form of the condition to achieve this minimal energy point. We also derive the closed form for computing the optimal SRP when the workloads follow a Gaussian distribution. We then study the joint workload allocation and computation frequency configuration problem for multiple distributed VMs scenario, and we propose solutions to solve the problem for both Gaussian and unspecified distributions. Our performance evaluation results on both synthetic and real-world workload trace data demonstrate the effectiveness of the proposed model. The closeness between the simulation results and the analytical results prove that our proposed method can achieve lower energy consumption compared with fixed computation capacity configuration methods.

An Adaptive Thermal Management Framework for Heterogeneous Multi-Core Processors

Off-the-shelf embedded systems have adopted heterogeneous multi-core processors which have high-performance big cores and low-power small cores. Though there are two different types of cores in heterogeneous multi-core processors, conventional DVFS (Dynamic Voltage and Frequency Scaling)-based DTM (Dynamic Thermal Management) techniques do not utilize the different types of cores to cool down hot cores. Rather, they primarily reduce the voltage and frequency of the hot cores, leading to performance degradation. In this article, we propose a novel adaptive DTM framework for heterogeneous multi-core processors, which utilizes the big and small cores to prevent performance degradation. Our proposed framework exploits two migration-based DTM techniques: 1) a technique (denoted as Migrationbig↔big) that migrates applications from hot big cores (big cores whose temperature is above a pre-defined threshold) to cold big cores (big cores whose temperature is below the threshold) and 2) a technique (denoted as Migrationbig↔small) that migrates all applications from the big cores to the small cores. In case of thermal emergency of the big cores, our proposed framework checks the number of cold big cores. When there exist available cold big cores, our proposed framework employs Migrationbig↔big to cool down the hot big cores while not reducing the big core frequency. On the other hand, when there does not exist any available cold big core, our proposed framework employs one between Migrationbig↔small and a DVFS-based DTM technique, which is expected to result in better performance. In our experiments on an embedded development board, our proposed framework improves the average performance by 8.9 percent, compared to ARM's DVFS-based IPA (Intelligent Power Allocation), satisfying thermal constraints. Our framework also improves the average performance by 10.4 percent, compared to a state-of-the-art predictive DVFS-based DTM technique.

Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode

Stringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, support for efficient design space exploration must be available in system level simulators. The advent of the edge computing paradigm, with power constraints in the mW domain, has rendered this even more essential. Without a fast and accurate methodology for architecture simulation and energy estimation, the benefit of new ideas and solutions cannot be evaluated. In this paper, we propose a non-intrusive application controlled DVFS management implementation in the GEM5 simulator, used with GEM5’s system call emulation mode. We also propose a novel architecture independent energy model based on categorization of different measurable workload classes. Our energy model is parametrized and calibrated with power measurements on a SAM4L microcontroller board, containing an ARM Cortex M4 processor. Together with the GEM5 output statistics, the model accurately estimates the total energy consumption of our simulated system. The results from our modified GEM5 simulator are validated with representative signal processing applications. After correction of systematic offset errors, our results deviate with less than 4% compared to measurements from the SAM4L microcontroller. Our contributions in this paper can easily be tailored to other processor models in GEM5 and to future versions of GEM5. It will therefore enable system architects to explore new techniques and compare the improvements relative to existing architectures.

Compact Thermal Modelling Tool for Fast Design Space Exploration of 3D ICs with Integrated Microchannels

Integrated microchannel cooling is a very promising concept for thermal management of 3D ICs, because it offers much higher cooling performance than conventional forced-air convection. The thermo-fluidic simulations of such chips are usually performed using a computational fluid dynamics (CFD) approach. However, due to the complexity of the fluid flow modelling, such simulations are typically very long and faster models are therefore considered. This paper demonstrates the advantages of TIMiTIC—a compact thermal simulator for chips with liquid cooling—and shows its practical usefulness in design space exploration of 3D ICs with integrated microchannels. Moreover, thermal simulations of a 3D processor model using the proposed tool are used to estimate the optimal power dissipation profile in the chip and to prove that such an optimal profile allows for a very significant (more than 10 °C) peak temperature reduction. Finally, a custom correlation metric is introduced which allows the comparison of the power distribution profiles in terms of the peak chip temperature that they produce. Statistical analysis of the simulation results demonstrates that this metric is very accurate and can be used for example in thermal-aware task scheduling or dynamic voltage and frequency scaling (DVFS) algorithms.

Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning

Energy efficiency has become a critical design metric for high-performance systems. Various power management techniques have been proposed for the processor cores such as dynamic voltage and frequency scaling (DVFS), whereas few solutions consider the power losses suffered on the power delivery system (PDS), despite the fact that they have a significant impact on the overall energy efficiency of the system. With the explosive growth of system complexity and highly dynamic workloads variations, it is also challenging to find the optimal power management policies which can effectively match the power delivery with the power consumption. In addition, process variations (PVs) add heterogeneity to systems and make traditional power management methods less effective. To tackle the above problems, we propose a reinforcement-learning-based Chip-Specific Power co-Management (CSPM) scheme for PV-aware manycore systems. Both PDS and processor cores are jointly adjusted by distributed agents with modular Q-learning to improve the overall energy efficiency of the system. System characteristics are naturally included in the learning process to obtain chip-specific policies. Experimental results show that when applied to PV-aware manycore systems with a hybrid PDS constructed by both on- and off-chip voltage regulators, the proposed method achieves a 60.1% reduction of the overall energy delay product (EDP) of the system, on average, compared to a traditional DVFS approach.

Energy-aware whale optimization algorithm for real-time task scheduling in multiprocessor systems

The growth of Multiprocessing Systems (MPS) has become a necessity for dealing with complex tasks and speeding up their execution. Increasing the number of processing cores on a single chip produces a vast processing power, but the biggest obstacle is the energy generated from these cores. The traditional techniques guarantee to get the optimal schedule, but they are costly in terms of time and memory storage. In this paper, we propose an Improved Whale Algorithm (IWA) to allocate the dependent tasks in MPS with two objectives minimizing the energy consumption and the makespan. The processing cores are assumed to support Dynamic Voltage and Frequency Scaling (DVFS) as an effective technique to reduce energy. The allocation of tasks in MPS is an NP-hard problem. Inadequate scheduling of tasks can result in consuming energy. Also, the failure to complete the tasks before their predetermined deadlines is a critical issue for real-time applications. We consider three different sources of energy coming from the communication, idle, and active states of the processing cores. We use an initialization procedure to produce a population of candidate schedules that respects the precedence among tasks. In IWA, we employ two different discretization methods to map the continuous values into discrete ones. Two specialized crossover operations are adopted to boost the quality of the candidate schedules while respecting the dependencies among the tasks. IWA implements the Load Balancing Improvement (LBI) strategy to alleviate the load of tasks from heavy cores. LBI plays a vital role in decreasing the static energy consumption. We compare IWA with the other algorithms, and the results show the superiority of IWA.

Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels

Energy optimization is an increasingly important aspect of today’s high-performance computing applications. In particular, dynamic voltage and frequency scaling (DVFS) has become a widely adopted solution to balance performance and energy consumption, and hardware vendors provide management libraries that allow the programmer to change both memory and core frequencies manually to minimize energy consumption while maximizing performance. This article focuses on modeling the energy consumption and speedup of GPU applications while using different frequency configurations. The task is not straightforward, because of the large set of possible and uniformly distributed configurations and because of the multi-objective nature of the problem, which minimizes energy consumption and maximizes performance. This article proposes a machine learning-based method to predict the best core and memory frequency configurations on GPUs for an input OpenCL kernel. The method is based on two models for speedup and normalized energy predictions over the default frequency configuration. Those are later combined into a multi-objective approach that predicts a Pareto-set of frequency configurations. Results show that our approach is very accurate at predicting extema and the Pareto set, and finds frequency configurations that dominate the default configuration in either energy or performance.