Dynamic Voltage And Frequency Scaling Research Articles

A tri-chromosome-based evolutionary algorithm for energy-efficient workflow scheduling in clouds

Cloud computing is increasingly attracting workflow applications, where workflows need to satisfy execution deadlines and energy consumption is to be minimized. So far, numerous studies have adopted evolutionary algorithms to optimize the energy consumption of workflow execution. Dynamic voltage and frequency scaling (DVFS) has been widely employed to save energy on computing devices running workflow tasks. However, most existing evolutionary algorithms focus on evolving task execution order or mapping from tasks to resources, while neglecting the evolution of task runtime to leverage the dynamic voltage and frequency scaling (DVFS) technology for further energy saving. To compensate for that deficiency, this paper designs a tri-chromosome-based evolutionary algorithm, namely TCEA, to evolve three types of decision vectors (i.e., task order, task and resource mapping, and task runtime) simultaneously using three problem-specific mechanisms. Firstly, we construct a search space by using the tasks’ minimum and optimal runtime, and propose a solution representation mechanism to simplify the decision vector for task runtime between 0 and 1. Secondly, we design a deadline constraint handling mechanism to distribute those durations exceeding the deadline to each task based on their extension of the minimum runtime. Thirdly, we exploit the workflow structure to cluster decision variables without direct constraints into the same group. During each iteration, only the order of tasks within a group evolves to avoid precedence constraints, thus performing searches within the feasible space. At last, we conduct comparison experiments on five types of real-world workflows with 30 to 1000 tasks. The energy consumed by TCEA is much less than those consumed by the state-of-the-art workflow scheduling algorithms, demonstrating the superior performance of TCEA in energy saving.

Energy Harvesting Deadline Monotonic Approach for Real-time Energy Autonomous Systems

This paper presents an innovative scheduling algorithm designed specifically for real-time energy harvesting systems, with a primary focus on minimizing energy consumption and extending the battery's lifespan. The algorithm employs a fixed priority assignment which is the deadline monotonic policy, we have chosen it for its optimality and superior performance compared to other fixed priority scheduling methods. To achieve a balance between energy efficiency and system performance, we incorporated a DVFS (Dynamic Voltage and Frequency Scaling) technique into the algorithm. This adaptive approach enables precise control over the processor's operating frequency, effectively managing energy consumption while ensuring satisfactory system functionality. The core objective of our scheduling algorithm centers on optimizing energy utilization in real-time energy harvesting systems, specifically tailored to extend the battery's operational life. Rigorous evaluations, including comprehensive comparisons against established fixed priority scheduling algorithms, validate the algorithm's efficacy in significantly reducing energy consumption while preserving the system's overall functionality. By combining the deadline monotonic policy and DVFS technique, our proposed algorithm emerges as a promising solution for energy-autonomous systems, contributing to the advancement of sustainable energy practices in real-time applications. As energy harvesting technologies continue to progress, our algorithm holds valuable potential to provide critical insights for enhancing the efficiency and reliability of future energy harvesting systems.

Dynamic Clock Switching Scheme for Enhanced Power Efficiency in System-on-Chip Architectures

High power consumption and thermal management are critical challenges in traditional System- on-Chip (SoC) architectures due to multiple active clock sources feeding individual IP blocks, even during idle states. This paper introduces a dynamic clock switching power-saving scheme that consolidates clock sources by dynamically switching to a single lower-frequency clock during low-power modes. A Clock Control Agent (CCA) monitors real-time operational status, power consumption, and performance needs, leveraging AI for predictive adjustments. Experimental results demonstrate a significant reduction in idle power consumption and improved thermal management, without compromising performance or data integrity. This scheme addresses inefficiencies in existing methods such as Dynamic Voltage and Frequency Scaling (DVFS) and clock gating, offering a robust and efficient solution for next-generation SoC designs.

Энергоэффективность многоядерных процессоров: сравнительное исследование аппаратных технологий

Background: The constant increase in processing demand has prompted the development of multi-core processors, which are critical to obtaining high performance in a variety of computing devices. However, this growth in processing capacity comes at the expense of increased energy consumption, posing substantial problems for energy efficiency. Objective: The article will examine and compare several hardware solutions for improving energy efficiency in multi-core processors, offering a full overview of their effectiveness and application. Methods: We used a quantitative research methodology, simulating multi-core processing environments with various hardware optimization techniques such as Dynamic Voltage and Frequency Scaling (DVFS), Clock Gating, and Power Gating. Each technique was evaluated in a variety of operational circumstances to establish its effect on energy consumption and processing efficiency. Results: The findings show that DVFS provides significant energy savings with negligible performance trade-offs in cases with moderate workloads. In contrast, Clock Gating performed best in low workload settings, whereas Power Gating performed best in high-load conditions, dramatically reducing idle power consumption. Conclusion: The comparison research demonstrates that no single technique beats all others; rather, the choice of an effective energy efficiency strategy is significantly influenced by unique workload factors. A hybrid strategy, which combines both techniques depending on real-time workload demands, can greatly improve the energy efficiency of multi-core processors. This study advances our understanding of energy management in advanced computing systems, providing insights for future research and practical applications in the field of energy-efficient computing.

A Novel Method for Optimising Energy Efficiency in High-Performance Computing Systems

This paper introduces a new method to promote energy efficiency in computing systems. The rapidly growing demand for computational power in high-performance computing (HPC) systems is accompanied by a significant increase in energy consumption. This research investigates the many ways to minimise energy consumption in HPC systems without sacrificing computational performance. Building upon previous research we combined and refined ideas to develop an optimised approach. Our method utilises a tri-modular framework incorporating an Energy-Efficient Hardware Design, Resource Management, and Optimisation, and Server Virtualisation. The first module employs a method of designing smart energy-efficient hardware. This method incorporates leakage reduction techniques such as clock gating and sleep states. The second module uses a technique focused on optimising server software. This method is based on Dynamic Voltage and frequency scaling (DVFS) for power management in data centres. The third module is based on server virtualisation and employs software to create multiple virtual machines on a single physical server allowing for a significant reduction in energy and hardware costs. The methods used in these three modules are systematically integrated to produce a more efficient consumption of electricity. This will allow for the computing system to minimise energy consumption without compromising computational power.

A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design

The demand for energy-efficient electronic devices has driven significant advancements in low-power Very-Large-Scale Integration (VLSI) design. This paper presents a Extensive review of the recent technologies and trends that have emerged to address the challenges associated with power utilization in VLSI circuits. The review covers a broad spectrum of innovations, including advanced transistor technologies such as FinFETs, Gate-All-Around (GAA) FETs, and Silicon-on-Insulator (SOI), which offer improved power efficiency. It also explores cutting-edge power enhance techniques like Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), highlighting their impact on reducing both dynamic and leakage power. Further, the paper examines energy-efficient architectures, including Near-Threshold Computing (NTC), approximate computing, and asynchronous circuits, which promise substantial power savings. The fusing of machine learning and AI in power optimization and the development of advanced Electronic Design Automation tools are also discussed as emerging trends. Finally, the paper considers future directions, including the potential of 3D Integrated Circuits (3D ICs), quantum and neuromorphic computing, and post-CMOS technologies, to revolutionize low-power VLSI design. This review provides a critical exploration of the actual state of the art and offers comprehensions into the future trajectory of low-power VLSI, making it a valuable resource for researchers and practitioners in the field.

An electricity price and energy-efficient workflow scheduling in geographically distributed cloud data centers

The cloud computing platform has become a favorable destination for running cloud workflow applications. However, they are primarily complicated and require intensive computing. Task scheduling in cloud environments, when formulated as an optimization problem, is proven to be NP-hard. Thus, efficient task scheduling plays a decisive role in minimizing energy costs. Electricity prices fluctuate depending on the vending company, time, and location. Therefore, optimizing energy costs has become a serious issue that one must consider when building workflow applications scheduling across geographically distributed cloud data centers (GD-CDCs). To tackle this issue, we have suggested a dual optimization approach called electricity price and energy-efficient (EPEE) workflow scheduling algorithm that simultaneously considers energy efficiency and fluctuating electricity prices across GD-CDCs, aims to reach the minimum electricity costs of workflow applications under the deadline constraints. This novel integration of dynamic voltage and frequency scaling (DVFS) with energy and electricity price optimization is unique compared to existing methods. Moreover, our EPEE approach, which includes task prioritization, deadline partitioning, data center selection based on energy efficiency and price diversity, and dynamic task scheduling, provides a comprehensive solution that significantly reduces electricity costs and enhances resource utilization. In addition, the inclusion of both generated and original data transmission times further differentiates our approach, offering a more realistic and practical solution for cloud service providers (CSPs). The experimental results reveal that the EPEE model produces better success rates to meet task deadlines, maximize resource utilization, cost and energy efficiencies in comparison to adapted state-of-the-art algorithms for similar problems.

Next-generation electronic devices: Innovations in integrated circuits, sensors, and computing architectures

This paper delves into the forefront of electronic engineering, showcasing the evolution of integrated circuits (ICs), sensor technology advancements, and the latest enhancements in microprocessors and microcontrollers. It underscores the significant strides made towards miniaturization, energy efficiency, and the integration of high-performance computing (HPC) within these devices. Through detailed examination, the paper highlights three pivotal areas: the revolutionary fabrication techniques enabling nanometer-scale ICs; the emergence of nano-sensing devices, wireless sensor networks (WSNs), and flexible sensors transforming the landscape of environmental monitoring and healthcare; and the development of energy-efficient architectures and security enhancements in microprocessors and microcontrollers. Employing quantitative analyses and mathematical models, the paper provides insights into the technological breakthroughs driving these advancements, including dynamic voltage and frequency scaling (DVFS), near-threshold computing (NTC), and the implementation of hardware-based security measures [1]. This comprehensive analysis not only illuminates the current state of electronic engineering but also outlines the potential future directions of the field, emphasizing the interdisciplinary approaches required to tackle the challenges of modern electronic device design and application.

An Implementation on Energy Efficient Task Scheduling in Cloud Environment

Abstract: Cloud computing has revolutionized the way computing resources are utilized by providing scalable, on-demand access to a shared pool of resources over the internet. It offers significant advantages such as cost savings, flexibility, and accessibility, making it an essential technology for businesses and individuals alike. However, the increasing energy consumption associated with cloud data centres has become a critical concern, necessitating the development of energy-efficient task scheduling algorithms. This paper explores various algorithms designed to optimize task scheduling in cloud environments to reduce energy consumption. Among these, heuristic algorithms like Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) are popular for their ability to find near-optimal solutions in large search spaces. Additionally, machine learning-based approaches, such as Reinforcement Learning (RL), have shown promise in dynamically adapting to workload variations and improving energy efficiency. Other notable algorithms include Ant Colony Optimization (ACO) and Dynamic Voltage and Frequency Scaling (DVFS), each offering unique mechanisms to balance performance and energy usage. The focus of this paper is on the implementation and comparative analysis of these task scheduling algorithms in a cloud environment. We present a comprehensive evaluation of their performance, highlighting their strengths and limitations in achieving energy efficiency. The results demonstrate that while no single algorithm is universally optimal, tailored combinations of these approaches can significantly enhance energy savings in cloud data centres.

Thermal Safe Power Constrained Dynamic Mapping for Heterogeneous Multicore System

Heterogeneous multicore system could provide high flexibility for applications through integrating different types of cores. As the number of cores increases, more and more transistors are integrated which could lead to the rise of chip temperature, thus have a negative impact on the system performance. At present, the typical method to tackle this problem is dynamic voltage and frequency scaling (DVFS) which reduces the voltage and frequency to achieve cooling. However, DVFS will make the heterogeneous multicore system unable to take full advantage of its performance. This paper proposes a dynamic mapping method called TspDM which maximizes the system performance target under the premise of satisfying the temperature safety power. TspDM exploits the runtime performance counters of running threads to dynamically adjust thread mapping. Specifically, a lightweight Artificial Neural Network (ANN) model is proposed to obtain the thread-to-core type mapping when a remapping process is activated. Subsequently, TspDM determines the specific core locations of threads according to the number of threads mapped to a certain core type and the thermal safety power computation. The experimental results show that the proposed method is 21% better than that of PCMig while ensuring the thermal safety of heterogeneous platform. In addition, TspDM outperforms recent performance constrained and power constrained literature in terms of system throughput.

An enhanced meta-heuristic algorithm used for energy conscious priority-based task scheduling problems in heterogeneous multiprocessor systems

The Task Scheduling Problem (TSP) in Multiprocessor Systems (MPS) is an emerging research area in heterogeneous distributed computing environments. Managing complex tasks and achieving optimal efficiency while scheduling tasks in MPS presents challenges. Although adding more processors to a single system greatly increases its processing power, the energy these processors produce is the main drawback. Here, we employed a multi-objective optimization strategy to reduce the makespan and Energy Consumption (EC). To reduce processor EC, we considered an effective Dynamic Voltage and Frequency Scaling (DVFS) technique. Three distinct energy sources are considered, originating from the processors' communication, idle, and active states. The scheduling sequence of tasks and the assignment of tasks to processors are two vital aspects of TSP. Here, the tasks are arranged based on priority using the Upward Rank technique. To minimize the makespan and EC while allocating tasks to processors, we use the population-based metaheuristic method called Enhanced Honey Badger Optimisation (EHBO). We proposed three improvements to the HBO algorithm in EHBO. Initially, we addressed opposite learning-based population initialization to exclude the least suitable candidates and generate a candidate scheduling population that adheres to task precedence. Subsequently, the levy-flight technique is employed to improve the local and global search and preserve their ideal healthy balance. Finally, using dynamic values rather than constant value improves the ability to obtain maximum food. Several experiments are conducted on random task graphs and real-life data sets. Additionally, the results are compared with other upgraded meta-heuristic algorithms, demonstrating the superiority of EHBO.

Energy-aware task scheduling for streaming applications on NoC-based MPSoCs

Streaming applications are being extensively run on portable embedded systems, which are battery-operated and with limited memory. Thus, minimizing the total energy consumption of such a system is important. We investigate the problem of offline scheduling for streaming applications composed of non-preemptible periodic dependent tasks on homogeneous Network-on-Chip (NoC)-based Multiprocessor System-on-Chip (MPSoCs) such that their total energy consumption is minimized under memory constraints. We propose a novel unified approach that integrates task-level software pipelining with Dynamic Voltage and Frequency Scaling (DVFS) to solve the problem. Our approach is supported by a set of novel techniques, which include constructing an initial schedule based on a list scheduling where the priority of each task is its approximate successor-tree-consistent deadline such that the workload across all the processors is balanced, a retiming heuristic to transform intra-period dependencies into inter-period dependencies for enhancing parallelism, assigning an optimal discrete frequency for each task and each message using a Non-Linear Programming (NLP)-based algorithm and an Integer-Linear Programming (ILP)-based algorithm, and an incremental approach to reduce the memory usage of the retimed schedule in case of memory size violations. Using a set of real and synthetic benchmarks, we have implemented and compared our unified approach with two state-of-the-art approaches, RDAG+GeneS (Wang et al., 2011) , and JCCTS (Wang et al., 2013a). Experimental results show that our approach’s maximum, average, and minimum improvements over RDAG+GeneS (Wang et al., 2011) are 31.72%, 14.05%, and 7.00%, respectively. Our approach’s maximum, average, and minimum improvement over JCCTS (Wang et al., 2013a) are 35.58%, 17.04%, and 8.21%, respectively.

Energy-efficient scheduling for parallel applications with reliability and time constraints on heterogeneous distributed systems

Reliability is a crucial index of the system, and many safety-critical applications have reliability requirements and deadline constraints. In addition, in order to protect the environment and reduce system operating costs, it is necessary to minimize energy consumption as much as possible. This paper considers parallel applications on heterogeneous distributed systems and proposes two algorithms to minimize energy consumption for meeting the deadline and satisfying the reliability requirement of the applications. The first algorithm is called minimizing scheduling length while satisfying the reliability requirement (MSLSRR). It first transforms the reliability requirement of the application into the reliability requirement of the task and then assigns the task to the processor with the earliest finish time. Since the reliability generated by MSLSRR is often higher than the reliability requirement of the application, and the scheduling length is also less than the deadline, an algorithm called improving energy efficiency (IEE) is designed, which redefined the minimum reliability requirement for the task and applied dynamic voltage and frequency scaling (DVFS) technique for energy conservation. The proposed algorithms are compared with existing algorithms by using real parallel applications. Experimental results demonstrate that the proposed algorithms consume the least energy.

Online Energy-Aware Scheduling for Deadline-Constrained Applications in Distributed Heterogeneous Systems

In the current computing environment, the significance of distributed heterogeneous systems has gained prominence. The research on scheduling problems in distributed systems that consider energy consumption has garnered substantial attention due to its potential to enhance system stability, achieve energy savings, and contribute to environmental preservation. However, efficient scheduling in such systems necessitates not only the consideration of energy consumption but also the ability to adapt to the dynamic nature of the system. To tackle these challenges, we propose an online energy-aware scheduling algorithm for deadline-constrained applications in distributed heterogeneous systems, leveraging dynamic voltage and frequency scaling (DVFS) techniques. First, the algorithm models the continuously arriving applications and heterogeneous processors and proposes a novel task-sorting method to prioritize tasks, ensuring that more applications are completed within their respective deadlines. Second, the algorithm controls the selection range of processors based on the task’s subdeadline and assigns the task to the processor with the minimum energy consumption. Through experiments conducted with randomly generated applications, our approach consistently exhibits superior performance when compared to similar scheduling algorithms.

LEC-MiCs: Low-Energy Checkpointing in Mixed-Criticality Multi-Core Systems

With the advent of multicore platforms in designing Mixed-Criticality Systems (MCSs), simultaneous management of reliability and energy while guaranteeing an acceptable service level for low-criticality tasks is a crucial challenge. To ensure the reliability of the MCSs against transient faults, fault-tolerant techniques are employed which will increase energy consumption. To mitigate the energy overhead, the Dynamic Voltage and Frequency Scaling (DVFS) technique will be exploited. However, this technique might lead to violating the timing constraints of high-criticality tasks. Therefore, this paper presents, for the first time, the low-energy checkpointing technique to guarantee the reliability of multiple preemptive periodic mixed-criticality tasks in a multicore platform. In contrast to the previous works in checkpointing technique which consider a specific number of faults that all the tasks in the system should tolerate, in this paper, the number of tolerable faults for each execution section of a task, and in each voltage and frequency level is determined through proposed formulas to meet the reliability target based on safety standards. Then, our proposed method determines the number of checkpoints and their non-uniform intervals for the normal and overrun sections of each task to reduce energy consumption, respectively. Moreover, the unified demand bound function (DBF) analysis is proposed for analyzing the schedulability of the task set, where each high-criticality task meets its timing and reliability constraints, and low-criticality tasks execute based on their derived guaranteed periods in each operational mode of the system. Experimental results show that our proposed scheme meets the timing and reliability constraints while at the same time, improving the QoS of low-criticality tasks, and managing energy consumption with an average of 29.49%, and 32.78%, respectively.

Architectural and Technological Approaches for Efficient Energy Management in Multicore Processors

Benchmarks play an essential role in the performance evaluation of novel research concepts. Their effectiveness diminishes if they fail to exploit the available hardware of the evaluated microprocessor or, more broadly, if they are not consistent in comparing various systems. An empirical analysis of the consecrated Splash-2 benchmarks suite vs. the latest version Splash-4 was performed. It was shown that on a 64-core configuration, half of the simulated benchmarks reach temperatures well beyond the critical threshold of 105 °C, emphasizing the necessity of a multi-objective evaluation from at least the following perspectives: energy consumption, performance, chip temperature, and integration area. During the analysis, it was observed that the cores spend a large amount of time in the idle state, around 45% on average in some configurations. This can be exploited by implementing a predictive dynamic voltage and frequency scaling (DVFS) technique called the Simple Core State Predictor (SCSP) to enhance the Intel Nehalem architecture and to simulate it using Sniper. The aim was to decrease the overall energy consumption by reducing power consumption at core level while maintaining the same performance. More than that, the SCSP technique, which operates with core-level abstract information, was applied in parallel with a Value Predictor (VP) or a Dynamic Instruction Reuse (DIR) technique, which rely on instruction-level information. Using the SCSP alone, a 9.95% reduction in power consumption and an energy reduction of 10.54% were achieved, maintaining the performance. By combining the SCSP with the VP technique, a performance increase of 8.87% was obtained while reducing power and energy consumption by 3.13% and 8.48%, respectively.

Dynamic Voltage and Frequency Scaling as a Method for Reducing Energy Consumption in Ultra-Low-Power Embedded Systems

Dynamic voltage and frequency scaling (DVFS) is a technique used to optimize energy consumption in ultra-low-power embedded systems. To ensure sufficient computational capacity, the system must scale up its performance settings. The objective is to conserve energy in times of reduced computational demand and/or when battery power is used. Fast Fourier Transform (FFT), Cyclic Redundancy Check 32 (CRC32), Secure Hash Algorithm 256 (SHA256), and Message-Digest Algorithm 5 (MD5) are focused functions that demand computational power to achieve energy-efficient performance. Selected operations are analyzed from the energy consumption perspective. In this manner, the energy required to perform a specific function is observed, thereby mitigating the influence of the instruction set or system architecture. For stable operating voltage scaling, an exponential model for voltage calculation is presented. Statistical significance tests are conducted to validate and support the findings. Results show that the proposed optimization technique reduces energy consumption for ultra-low-power applications from 27.74% to up to 47.74%.

Artificial Intelligence Driven Power Optimization in IOT-Enabled Wireless Sensor Networks

The widespread use of Wireless Sensor Networks (WSN) in Internet of Things (IoT) causes energy efficiency issues. This paper proposes an AI-based solution to this problem. The propose an AI-Driven Power Optimization framework for IoT-enabled WSN using Deep Q-Network (DQN) and Dynamic Voltage and Frequency Scaling (DVFS). These techniques can adapt to changing network conditions and reduce power consumption when used together. Sensor nodes provide environmental parameters, battery status, and network behavior data to the AI-driven framework DQN is implemented after data preprocessing to learn and make power management decisions using reinforcement learning. Neural network-driven agent operates in a state and action space. It optimizes energy use with rewards. Real-time hardware power adjustment is done using DVFS. DVFS precise control and AI-driven decision-making create a comprehensive power optimization strategy. AI adapts to new challenges and optimizes network lifespan by improving its power management policies. Experimental implementations of the proposed framework show significant energy savings, network lifespan extension, and QoS improvements. AI-Driven Power Optimization in IoT-enabled WSN is proven effective and flexible. This study shows the potential of AI, specifically DQN and DVFS, in IoT-enabled WSN. This AI-Driven Power Optimization framework addresses energy efficiency and improves IoT sensor networks. AI improves power optimization in IoT-enabled WSN making IoT deployments more sustainable and resilient.

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

This article tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms. Applications are composed of directed acyclic graphs of tasks, with each directed-acyclic-graph (DAG) having a minimum inter-arrival period for its activation requests and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multi-core platforms with Dynamic Voltage and Frequency Scaling (DVFS) capabilities, including big.LITTLE Arm architectures and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by minimizing power consumption, respecting precise timing constraints, maximizing the applications’ slack, respecting given power consumption constraints, or even a combination of these, in a multi-objective formulation. We propose an off-line optimization of the mentioned problem based on mixed-integer quadratic constraint programming (MIQCP). The optimization provides the DVFS configuration of all the CPUs (or accelerators) capable of frequency switching and the placement to be followed by each task in the DAGs, including the software-vs.-hardware implementation choice for tasks that can be hardware accelerated. For relatively big problems, we developed heuristic solvers capable of providing suboptimal solutions in a significantly reduced time compared to the MIQCP strategy, thus widening the applicability of the proposed framework. We validate the approach by running a set of randomly generated DAGs on Linux under SCHED_DEADLINE, deployed onto two real boards, one with Arm big.LITTLE architecture, the other with FPGA acceleration, verifying that the experimental runs meet the theoretical expectations in terms of timing and power optimization goals.

Energy saving of cluster computing by CPU frequency Tuning using genetic algorithm

Dynamic voltage and frequency scaling (DVFS) is a tool used primarily to decrease computer processor energy consumption by lowering its operational frequency. Their only downside is that they distract from the efficiency of parallel applications while operating on parallel platforms. In a heterogeneous cluster architecture, however, a genetic algorithm is being implemented and applied to model the best trade-off between energy-saving and parallel application performance degradation. The proposed algorithm selects the best frequency vector in order to accomplish these objectives by providing the same compromise. So, the objective function of the genetic algorithm at the same time gives limited energy consumption and minimum decreases in performance. The SimGrid simulator will be used for all experiments. The suggested algorithm saves the average energy by (20 %) and the application performance degrades to the limit (0.15 %).