Dynamic Threshold Voltage MOSFET Research Articles

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

A New Low-Voltage Second Generation Voltage Conveyor Using Merged Voltage Follower and DTMOS Techniques

A very simple, compact and low-power second generation voltage conveyor circuit using only eight transistors is proposed in this work. Voltage follower stage is implemented using merged voltage follower (MVF), offering very low output impedance. A simple current mirror forms the input stage of the proposed voltage conveyor. To further enhance the linearity, another circuit is proposed where input transistor in MVF is replaced with DTMOS (Dynamic Threshold Voltage MOSFET), giving [Formula: see text][Formula: see text]mV linearity range as compared to [Formula: see text][Formula: see text]mV of the first proposal. Proposed-II VCII provides reduced offset voltage due to decreased effective threshold of DTMOS, and gain bandwidth product of the circuit also improves. Simulation results are computed using 180-nmCMOS technology with supply voltage of [Formula: see text][Formula: see text]V to validate the proposed circuits. Proposed-I and proposed-II VCII consume 85.1[Formula: see text][Formula: see text]W and 97.5[Formula: see text][Formula: see text]W, respectively. An application of the proposed conveyors as “current to voltage converter”, is also presented.

A four-quadrant analog multiplier using DTMOS for low power applications

ABSTRACT The four-quadrant analog multipliers (FQAM) are widely used in signal processing applications such as amplitude modulation, frequency doubling, and adaptive filters. In this paper, a FQAM has been realised in dynamic threshold voltage MOSFET (DTMOS) technology. It relies on the square-law characteristics of the MOS transistor. Several simulations have been carried out to assess the operation of the proposed FQAM. The supply voltage is set to ±0.2 V, and 68 µW power consumption is determined. The input signal can be applied to the full scale of the supply voltage. The bandwidth is 22.86 MHz, and the output signal’s total harmonic distortion (THD) is less than 2%. Intermodulation products of the output signal have been calculated. Monte Carlo and temperature simulations have been performed in a way that confirms the robustness of the circuit against the technological spread. In summary, low power consumption, wide bandwidth, and linearity are the advantages of the proposed circuit.

Operational Amplifier Design Employing DTMOS Technique with Dual Supply Voltages

An operational amplifier (OPAMP) for portable devices with dual supply voltage is presented in this work. The design is realized with a 600[Formula: see text]mV supply for the core design and a 1.8[Formula: see text]V supply for the biasing circuit to improve input common mode range (ICMR), gain, and common mode rejection ratio (CMRR). The designed amplifier is implemented with dynamic threshold voltage MOSFET (DTMOS) transistors to decrease power consumption and increase the performance of the design. The power consumption of the core design is obtained as 2[Formula: see text][Formula: see text]W while the biasing circuitry consumes 7.38[Formula: see text][Formula: see text]W. The application of different supply voltages has greatly increased the gain of the circuit, where the circuit exhibits 100.2[Formula: see text]dB DC gain and 3.41[Formula: see text]MHz gain bandwidth product (GBW). CMRR of the designed circuit is 84.22[Formula: see text]dB. The simulations are performed in Cadence environment with 0.18[Formula: see text][Formula: see text]m CMOS technology.

A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier

The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising a flip voltage follower is used which boosts the dynamic current and gain-bandwidth product of OTA. Conventional current mirrors are replaced with source degenerated non-linear current mirrors to achieve a better slew rate. The conventional and proposed RFC structures are designed and simulated in a standard 180 nm CMOS process at 1 V supply voltage. The proposed RFC OTA demonstrates a significant enhancement in the performance parameter as 11 dB improvement in the gain as well as 290% more GBW and achieves a slew rate that is nine times better compared to the conventional RFC.

Realization of DTMOS based CFTA and multiple input single output biquadratic filter application

Analog filters can be found in everything from mobile phones to disk drives, from audio systems to power supplies, from telecommunications to broadband internet connection. Analog filters can be formed from a variety of active elements. In this study, the Dynamic Threshold Voltage MOSFET (DTMOS) based Current Follower Transconductance Amplifier (CFTA) active element has been suggested and a multi input single output (MISO) universal biquadratic filter has been obtained with this active element. The proposed circuit operates with ±0.2 V supply voltages and consumes 140 µW power and electronically tunable. All five filtering responses have been realized by selecting the different input signals. All simulations have been performed with LTSpice program using the Predictive Technology Model (PTM) 45 nm Level 54 CMOS process parameters. Analysis of AC/DC, noise, Monte Carlo, temperature, total harmonic distortion (THD) proves that the circuit operates in harmony with the theory. With Monte Carlo analysis, it has been observed that the filter achieves stable output against both passive element and process parameter tolerance. It is hoped that the proposed active element and the filter will be useful in ultra-low voltage, low power, and low frequency analog signal applications.

Impact of subthreshold slope on sensitivity of square law detector for high frequency radio wave detection

An impact of subthreshold slope on sensitivity of square law detectors composed of an FET has been investigated. Theoretical consideration starting from the unified charge control model of FET channel carriers comes down to formulae which indicate that the subthreshold slope significantly affects output voltage and sensitivity of the square law detector. Experiments carried out to detect gigahertz waves using a MOSFET which has a body terminal isolated from other terminals and, therefore, is able to operate as the dynamic threshold voltage MOSFET show the significance of the subthreshold slope. Verification performed by detecting terahertz waves using HEMT detectors also proves the theoretical conclusion and almost agrees with detection characteristics predicted from derived mathematical formulae.

A Near-Zero-Power Wake-Up Receiver Achieving −69-dBm Sensitivity

This paper presents the design of a wake-up receiver (WuRX) that both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an off-chip impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator. Implemented in a 180-nm silicon on insulator CMOS process using dynamic threshold-voltage MOSFET (DTMOS) devices, the OOK-modulated WuRX operates at 113.5 MHz and achieves a sensitivity of −69 dBm, while consuming just 4.5 nW from a 0.4-V supply.

Design of low power DTMOS based FCS and its notch filter application for ECG signals

In this study, p-MOSFETs in floating current source circuit are converted to dynamic threshold voltage MOSFET structure and a second order notch filter application is carried out by using the DTMOS based FCS circuit. The proposed model is simulated in LTSPICE simulator by using Taiwan Semiconductor Manufacturing Company 0,18μm CMOS technology. DTMOS structure allows the operation of the circuit at lower power about 4,95nW. Operating frequency of notch filter consisting of the DTMOS-FCS circuit is set up to suppress the undesirable effects of power-line interference on the electrocardiograph signals.

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations.

Evaluation of a New Hybrid Technique Based on DTMOS and PFA to Improve Supply Voltage and Power Consumption of a Class-AB Amplifier

In this paper, two useful techniques of Dynamic Threshold Voltage MOSFET (DTMOS) and Positive Feedback Amplifier (PFA) are investigated separately and are applied simultaneously on a Class-AB Amplifier in the 180 nm CMOS technology. In the first proposed technique, Simulation results show that operating voltage can be limited to ±0.5 V in which the voltage gain and bandwidth are 52.6 dB and 103.51 MHz, respectively. In the second proposed technique, the power consumption is reduced more than 50%, the open-loop gain is enhanced 47% and Common Mode Rejection Ratio (CMRR) improves to 86.5 dB. By applying combination of these two techniques for designing the amplifier, CMRR increases to 92.1 dB and the power consumption reduces to 97 µW with the bandwidth of 59.12 MHz.

High Efficiency Buck-Converter with Short Circuit Protection

This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Thresholdvoltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

Measurement and Analysis of PD-SOI Static Latches Based on Bistable-Gated-Bipolar Device

Bistable-gated-bipolar (BGB) device is an impact-ionization based negative differential resistance (NDR) device featuring full process compatibility with CMOS. This paper presents measurement and analysis of the BGB-based static latches fabricated in a standard 0.35 partially depleted silicon-on-insulator (PD SOI) CMOS technology. The experimental results demonstrate the static storage functionality and the minimum standby current of 0.1-1 nA per BGB device for the drain-to-source voltage ranging from 2.0 to 1.6 V. Compared with the conventional CMOS static latch in the same technology, the delay time is shortened by 100 ps, verified by measurement, SPICE simulation and analysis. As the major penalty for speed enhancement, increase in standby current prevents the BGB devices and the associated MOS switches from aggressively scaling and the BGB-based latches are suitable for large-geometry CMOS logic and ultralow-voltage dynamic threshold voltage MOSFET (DTMOS) logic with high switching activity.

1 V fully balanced differential amplifiers: Implementation and experimental results

We report a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier, which are based on Dynamic Threshold voltage MOSFET (DTMOS) transistors. Pseudo P type DTMOS transistors are used to enhance the differential input common-mode range. The proposed circuits were fabricated using standard CMOS 0.18 μm CMOS process technology. The fully differential class AB amplifier is implemented to enhance the noise performance of low voltage high precision switched capacitor circuits, the fully balanced preamplifier is implemented to drive the differential inputs of the analog to digital converter used in the analog front-end of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. The power consumption of the proposed preamplifier is only 80 μW. The minimum experimental supply voltage is roughly 0.8 V.

Behavior of a traveling-wave amplifier versus temperature in SOI technology

In this paper, the design and measurement results of a CMOS partially depleted silicon-on-insulator (SOI) traveling-wave amplifier (TWA) are presented. The four-stage TWA is designed with a single common source nMOSFET in each stage using a 130-nm SOI CMOS technology requiring a chip area of 0.75 mm/sup 2/. A gain of 4.5 dB and a unity-gain bandwidth of 30 GHz are measured at 1.4-V supply voltage for a power consumption of 66 mW. The designed circuit has been characterized over a temperature range from 25 /spl deg/C to 300 /spl deg/C. The performance degradation on the gain of the TWA, the SOI transistors, as well as the microstrip lines used for the matching network are analyzed. Thanks to the introduction of a dynamic threshold-voltage MOSFET, a greater gain-bandwidth product under lower bias conditions is demonstrated.

0.6 V D flip-flop utilising negative differential resistance device

A novel D flip-flop for low voltage operation with improved speed isproposed using SPICE simulation, which takes advantage of a dynamic threshold voltage MOSFET featuring ultra-low voltage operation and a negative differential resistance storage featuring less capacitance.

A novel dynamic threshold Voltage MOSFET (DTMOS) using heterostructure channel of Si/sub 1-y/C/sub y/ interlayer

We have demonstrated the fabrication of dynamic threshold voltage MOSFET (DTMOS) using the Si/sub 1-y/C/sub y/(y=0.005) incorporation interlayer channel. Compare to conventional Si-DTMOS, the introduction of the Si/sub 1-y/C/sub y/ interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. This novel Si/sub 1-y/C/sub y/ channel heterostructure MOSFET exhibits higher transconductance and turn on current.

High-Voltage and High-Temperature Applications of DTMOS With Reverse Schottky Barrier on Substrate Contacts

In this letter, for the first time, application of dynamic threshold voltage MOSFET (DTMOS) with reverse Schottky barrier on substrate contacts (RSBSCs) for high voltage and high temperature is presented. By this RSBSC, DTMOS can be operated at high voltage (>0.7 V), and exhibits excellent performance at high temperature in terms of ideal subthreshold slope, low threshold voltage and high driving current.

A Novel Low-Voltage N-Channel Heterostructure Dynamic Threshold Voltage MOSFET (N-HDTMOS) With p-Type Doped SiGe Body

A novel N-channel Si/SiGe heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) has been proposed and fabricated. The Si/SiGe N-HDTMOS consists of an unstrained surface Si channel and heavily p-type doped SiGe body. The potential of the conduction band edge of the surface Si channel can be lowered by introducing a heavily p-type doped SiGe layer into a suitable position in the body region. As a result, the N-HDTMOS shows a threshold voltage reduction and a body effect factor (/spl gamma/) enhancement while keeping high doping concentration in the SiGe layer. The fabricated SiGe N-HDTMOS exhibits superior properties, that is, 0.1 V reduction of V/sub th/, 1.5 times enhancement of /spl gamma/, and 1.3 times saturated current, as compared with those of Si N-DTMOS.

A two-dimensional physically-based current model for deep-submicrometer SOI dynamic threshold-voltage MOSFET

An improved physically-based model for deep-submicrometer SOI dynamic threshold-voltage MOSFET (DTMOS) is proposed in this paper, considering the mobile charge determined by both the forward base bias and the gate controlling for quasi-two-dimensional analysis. The alleviated dependence of the surface potential on the channel length and the drain voltage is described, as well as the unique dynamic characteristics of the threshold voltage and threshold-voltage shift for DTMOS. Key physical effects, including velocity saturation effect, mobility degradation effect and channel length modulation effect influenced by the dynamic threshold voltage, are involved in this model. The model is verified by the comparison between the model predictions, numerical results and experimental data of SOI DTMOS devices with various geometries.