Abstract
The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations.
Highlights
Ultra-low-voltage (ULV) operation is a popular design approach to achieve high energy efficiency
In spite of the performance advantages previously discussed, gate level body biasing (GLBB) logic gates show somewhat increased leakage current with respect to their zero body-biased (ZBB) CMOS and dynamic threshold voltage MOSFET (DTMOS) counterparts. This is mainly due to the fact that the output voltage transition of the body biasing generator (BBG) is not rail-to-rail
A preliminary analysis performed on simple logic gates demonstrates that the speed boosting provided by the suggested approach allows ULV GLBB circuits to reach performances which are unaffordable for both conventional CMOS and DTMOS configurations
Summary
Ultra-low-voltage (ULV) operation is a popular design approach to achieve high energy efficiency. A major limitation for the use of bulk DTMOS devices is that a large distance between transistors controlled by different gate signals has to be maintained to ensure correct body isolation between differently body-biased devices [14, 15] This causes a higher occupied silicon area and longer interconnections which in turn degrade speed and energy performances. It is worth noting that postlayout analysis is strictly required when adaptive body biasing techniques are used in nanometer technologies This is because the physical distances needed to provide correct body isolation between differently body-biased devices have a very large impact on delay and energy characteristics of the circuits. Depending on power supply voltage level, the GLBB FA allows delay to be reduced in the ranges of 6%–34% and 24%–40% in comparison to the ZBB CMOS and DTMOS circuits, respectively This is achieved saving energy per operation.
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