Dynamic Threshold MOSFET Research Articles

Dynamic Threshold MOSFET Based Comparators

Dynamic Threshold MOSFET Based Comparators

Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits

By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology.We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques.

RF Energy Harvesting using Cross-couple Rectifier and DTMOS on SOTB with Phase Effect of Paired RF Inputs

In this paper, the design and evaluations of a cross-couple rectifier (CCR) with floating sub-circuit using Dynamic Threshold MOSFET (DTMOS) for RF energy harvesting is presented. The circuit is fabricated using 65nm Silicon on Thin Buried Box (SOTB) CMOS technology. The measurement result shows that circuit exceeds 1000 mV DC output at -14 dBm input power and obtains 48 % power conversion efficiency (PCE) at a level of -10 dBm input power. The proposed circuit generated 0.9 μW DC output power at a level of -21 dBm input power which equivalent to 10.6 % PCE when harvesting the 950 MHz LTE signal in the ambient environment. The study also indicates the effect of phase difference between the two RF input signals on the DC output voltage in CMOS CCR. The DC output voltage depends on the phase of the two RF input signals and reaches a maximum when the phase difference between the two RF signals is π. Experimental results demonstrate that the output voltage changes from 950 mV to -100 mV when the phase difference varies from π to 0 at an RF input power of -10 dBm. When the rectifier receives an RF signal from the environment at an input power of -21 dBm, the DC output voltage changes from 300 mV to -50 mV when the phase changes from π to 0.

DTMOS based Gilbert mixer design for MICS receiver using current source helpers and switched biasing technique

In this paper, dynamic threshold MOSFET (DTMOS) based down conversion Gilbert mixer is proposed for medical implant communication services (MICS) receiver design using UMC 180 nm CMOS process. The current source helpers and switched biasing technique are used to progress the performance of the DTMOS based Gilbert mixer. The proposed design operates at a radio frequency (RF) of 403 MHz with a maximum conversion gain of 12.5 dB at 5 dBm of LO power. The 1 dB compression point and third order input intercept point (IIP3) for the proposed design is − 8.79 dBm and 3.92 dBm respectively, with a noise figure (NF) of 6.6 dB at an intermediate frequency (IF) of 10 MHz. This design circuit works in 0.9 V supply voltage and consumes a dc power of 0.55 mW with the chip area of 0.035 × 0.037 mm2. So, this design with high conversion gain and better noise performance is a suitable block for MICS applications.

A 2.77 μW Ambient RF Energy Harvesting Using DTMOS Cross-Coupled Rectifier on 65 nm SOTB and Wide Bandwidth System Design

This paper proposes a structure of the μ W RF energy harvesting (RFEH) system that is used for scavenging RF power from an ambient environment. A cross-coupled rectifier (CCR) with floating sub-circuit structures was utilized in the application of dynamic threshold MOSFET (DTMOS) on Silicon on Thin Buried Oxide (SOTB) to obtain high drain conductance of the MOSFET. A wide bandwidth matching between antenna and rectifier was designed to receive energy from the orthogonal frequency division multiplexing (OFDM) RF signal with a bandwidth of 15 MHz at 950 MHz band. Realistic measurements with a 950 MHz LTE mobile phone signal from the ambient environment indicate that an average DC output power of 2.77 μ W is harvested with the proposed RFEH system at a level of −19.4 dBm input power. The proposed RFEH system exhibits the best performance when compared to that of other realistic RFEH systems and is a potential candidate for battery-less Internet of Things (IoT) applications.

Dynamic Threshold MOSFET for Low Power VLSI Circuit Design

Dynamic Threshold MOSFET for Low Power VLSI Circuit Design

동적 문턱전압 MOSFET를 사용한 새로운 저전압 저전력 셀프 캐스코드 구조의 설계 및 응용

본 논문에서는 동적 문턱전압 MOSFET를 사용한 새로운 셀프 캐스코드 구조의 설계방식을 제안한다. 제안한 셀프 캐스코드는 저전압 및 저전력 소비를 위하여 공급전압이 500mV인 약반전 영역에서 동작하며 이 구조는 기존의 구조들에 비하여 칩 면적이 매우 작고 DC 바이어스 전압이 요구되지 않는다. 또한 동적 문턱전압 MOSFET의 특성에 의하여 트랜스컨덕턴스 (출력저항)는 단일 MOSFET 및 기존의 셀프 캐스코드에 비하여 각각 45%(163%), 24%(80%) 이상 증가한다. 본 논문에서 제안한 설계방식의 타당성을 검증하기 위하여, 기존 및 제안한 셀프 캐스코드들에 의하여 전류미러를 설계하였다. 모의실험은 Cadence 툴에 의하여 TSMC 0.18 ㎛ CMOS 공정을 사용하여 수행되었다. 모의실험 결과, 본 논문에서 제안한 방식으로 설계한 전류미러의 출력 전압에 대한 출력전류의 변동률이 20배 이상 향상되었다.

A low phase noise gm-boosted DTMOS VCO design in 180 nm CMOS technology

This paper presents the design of a low phase noise voltage controlled oscillator (VCO), which offers higher transconductance (gm) by the use of parallel MOSFETs. Here, two NMOS transistors are connected in parallel with the cross-coupled NMOS transistors of a conventional cross-coupled VCO. So, the total negative conductance offered to the circuit to cancel out the parasitic resistance of the LC-tank is increased. This negative conductance is achieved without dealing with larger transistor size or any other passive elements. Hence, power dissipation and silicon area are reduced. Further, dynamic threshold MOSFET (DTMOS) with a capacitive division technique is implemented to increase the voltage swing, leading to a further decrease in phase noise. The proposed VCO is designed and simulated in UMC 180 nm technology. It achieves a tuning range of 1.58–1.60 GHz about 200 MHz, with 6.09 mW power consumption at 1.1 V supply voltage. The phase noise is obtained −40.6 dBc/Hz at 1 kHz and −120.44 dBc/Hz at 1 MHz respectively. So, it should be used in transceiver and PLL blocks for low voltage and low phase noise applications.

Design of low power 10GS/s 6-Bit DAC using CMOS technology

A Low power 6-bit R-2R ladder Digital to Analog Converter is presented in this paper. Here the R-2 R network designed using resistors with only two values-R and 2xRand the switch is designed by using both NMOS and PMOS Transistors. This Digital to Analog Converters operated with low voltage, by applying dynamic threshold MOSFET (DTMOS) logic. This design achieved less INL and DNL which is 0.3 and 0.06 respectively. Power supply required to operate this device is only 1V with10GHzconversion rate. This design is implemented by using 0.18μm CMOS technology.

DTMOS-Based Pulse Transformer Boost Converter With Complementary Charge Pump for Multisource Energy Harvesting

An energy-harvesting system that accommodates both discrete-time or continuous-time energy sources simultaneously is presented. The core dc–dc converter is a pulse transformer boost converter using dynamic threshold MOS transistor that self-starts at 36 mV-input voltage and generates bipolar output voltages up to ±2.5 V. Employing the dynamic body bias technique to the boost converter power transistor improves power efficiency at sub-300-mV input voltages up to two times over the identical transistor in a conventional configuration. At large harvested power, the source-to-body diode of the power transistor functions as an input voltage limiter. Dynamic threshold MOSFET (DTMOS) also increases transistor saturation current and output power compared to conventional transistors at similar input voltage. Instead of using a linear shunt regulator, excess power is dissipated by internal loss of a bipolar-clocked cross-coupled charge pump. An on-chip voltage-controlled oscillator, which generates clock frequency in proportion to the harvested power, and a unipolar-to-bipolar level shifter are included to drive the charge pump designed. The circuit prototypes are fabricated by using the UMC 0.13- $\mu\mbox{m}$ CMOS process with the triple-well option.

A Design of Modulator and Demodulator for a Passive UHF RFID Tag Using DTMOST Compatible with C1 G2 EPC Standard Protocol

This paper presents a modulator and low power ASK demodulator that uses a new technique. This technique uses the dynamic threshold MOSFET to reduce the threshold voltage of diodes connected MOS transistors as a barrier in the design of the envelope detector. This circuit has been simulated in a 90 nm CMOS technology to satisfy EPC Class 1 Generation 2 standard protocol. The proposed circuit can correctly demodulate the minimum input power −20 dBm for a modulation index of 37–100 % with 40–160 kb/s data rates. The proposed technique has reduced energy consumption at 11.44 nW at 0.4 V, 27 °C. This will increase the operating range of the RFID tags.

A 0.7 V Relative Temperature Sensor With a Non-Calibrated <formula formulatype="inline"><tex Notation="TeX">$\pm 1~^{\circ}{\rm C}$</tex></formula> 3<formula formulatype="inline"><tex Notation="TeX">$\sigma$</tex></formula> Relative Inaccuracy

This paper presents a new low-voltage relative temperature sensor for multi-core digital processor on-chip thermal management in a 180 nm CMOS process. Three types of sensing diodes including Schottky barrier diode (SBD), subthreshold MOSFET diode and dynamic threshold MOSFET (DTMOS) diode have been investigated for low-voltage operation, while traditional parasitic PNP-bipolar junction transistor (BJT) diodes are implemented to provide a performance reference. A matrix of 7 $\times$ 7 small remote sensor nodes is implemented on the chip with a deployment density of 49/0.81 ${\rm mm}^{2}$ and sharing the same bias current generator, control logic, and data converter. The measured minimum supply voltage (not including the clock control block) of the sensor is 0.7 V over $-55~^{\circ}{\rm C}$ to 125 $~^{\circ}{\rm C}$ . The relative sensing inaccuracies $(3\sigma)$ without calibration are less than $\pm 1.5~^{\circ}{\rm C}$ , $\pm 1.2~^{\circ}{\rm C}$ and $\pm 1~^{\circ}{\rm C}$ for the designs based on SBD, subthreshold MOSFET, and DTMOS, respectively. To the best of the authors’ knowledge, this is the first time that non-calibrated relative sensing accuracy is reported for SBD-based and DTMOS-based temperature sensors, and the best reported result for the design based on subthreshold MOSFET. The absolute inaccuracies with calibration-per-chip are also presented. Furthermore, the multi-location thermal monitoring function has been experimentally demonstrated and a 1.8 $^{\circ}{\rm C/mm}$ on-chip temperature gradient was detected.

0.5-V DTMOS median filter

This letter presents an analog median filter with ultra-low-voltage supply and extremely low-power consumption. The structure of the median filter is based on comparators built by current limiting transconductance amplifier (OTA). In order to achieve high transconductance and large input range the proposed CMOS structure of the OTA is based on a cascade of two differential stages where the differential pairs exploit the dynamic threshold MOSFET (DTMOS) technique. The proposed structure of OTA is capable to work with 0.5V supply voltage and consumes 30nW with simple CMOS circuitry. The design and simulation of the median filter have been performed in Cadence environment using the 0.18μm CMOS TSMC process. The simulation results prove the functionality and the attractive features of the proposed circuit.

Analog Performance At Room and Low Temperature of Triple-Gate Devices: Bulk, DTMOS, BOI and SOI

In this paper, the analog performance of Bulk, DTMOS (Dynamic Threshold MOSFET - DT), BOI (Body-On-Insulator) and SOI (Silicon-On-Insulator) triple-gate devices is compared through three-dimensional numerical simulations. Furthermore, the impact of low temperature operation was also studied for different channel doping concentrations. The results indicate that DTMOS structures show the best analog performance for higher channel doping concentration at room temperature and they present a larger transistor efficiency (gm /ID) at all temperatures analyzed. In spite of the gm/ID improvement at low temperatures for all structures, the Early voltage and intrinsic voltage gain degrade for Bulk and DTMOS devices when the channel doping concentration is high. For lowly doped channels, the Early voltage and intrinsic voltage gain increase at lower temperature in all structures studied with a slight improvement for the SOI devices.

A 1.6-V 17-µA 5.2-ppm/°C bandgap reference with mutative curvature-compensation

A high-precision high-order curvature-compensated bandgap reference (BGR) compatible with standard BiCMOS process is presented in this article. By utilising the subthreshold and substrate currents generated by only a dynamic-threshold MOSFET (DTMOS), a novel mutative curvature-compensation has been realised to reduce the temperature drift within the full temperature range. The proposed mutative curvature-compensation is achieved by a high-order compensation term with changed temperature characteristics in the temperature range. Verification results of the proposed BGR implemented with 0.25 µm BiCMOS process demonstrate that the proposed BGR can operate down to 1.6 V supply voltage and consume a maximum supply current of 17 µA. A temperature coefficient of 5.2 ppm/°C is realised with temperature ranging from −65°C to 140°C, and a power supply rejection ratio of 57.7 dB is achieved without filtering capacitors.

A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme

Combined with partial dynamic threshold MOSFET connection scheme, a high density 7T subthreshold SRAM bitcell operating at supply voltage of 200 mV is proposed in this paper. Dual write and single read ensures high read static noise margin of the SRAM bitcell without expense of writability degradation. The 7T SRAM exhibits robust efficiency, making the design less vulnerable to process variation. Compared to the referenced 6T and the 8T SRAM bitcell, the proposed bitcell has four aspects of improvement: (1) 5.1% and 6.1% larger hold margin, (2) 80.6% and 85.5% of standard deviation, (3) 50% and 18% reduction of area (at 200 mV), and (4) 16X and 32X bitcells per bitline. To our best knowledge, the area penalty of proposed SRAM is the smallest with robustness and functionality of subthreshold SRAM achieved.

A 0.3 V Cross-Coupled VCO Using Dynamic Threshold MOSFET

An ultra-low voltage differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 ? m CMOS 1P8M process. The designed circuit topology is an nMOS-core cross-coupled LC-tank VCO, and a self-generated 2nd harmonic ac signal is coupled to the bodies of MOSFETs to enhance the VCO performance. At the supply voltage of 0.3 V, the output phase noise of the VCO is -116.88 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 3.579 GHz, and the figure of merit is -194.43 dBc/Hz. Total power consumption is 0.225 mW. Tuning range is about 240(770) MHz, from 3.39 to 3.63(4.16) GHz, while the control voltage was tuned from 0 V to 0.3(1.0) V.

A novel SOI-DTMOS structure from circuit performance considerations

The performance of a partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DT-MOS) is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOI DTMOSFET structure (drain/source-on-local-insulator structure) is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.

Design and Analysis of UHF Micropower CMOS DTMOST Rectifiers

Design and analysis of ultrahigh-frequency (UHF) micropower rectifiers based on a diode-connected dynamic threshold MOSFET (DTMOST) is discussed. An analytical design model for DTMOST rectifiers is derived based on curve-fitted diode equation parameters. Several DTMOST six-stage charge-pump rectifiers were designed and fabricated using a CMOS 0.18-mum process with deep n-well isolation. Measured results verified the design model with average accuracy of 10.85% for an input power level between -4 and 0 dBm. At the same time, three other rectifiers based on various types of transistors were fabricated on the same chip. The measured results are compared with a Schottky diode solution.

Wide‐locking range divide‐by‐4 injection‐locked frequency dividers

AbstractThis article studies two wide‐locking range divide‐by‐4 injection locked frequency dividers (ILFDs) employing tunable active inductor (TAI), which are used to extend the locking range and to reduce die area. The CMOS differential ILFD is based on a TAI‐C tank Colpitts voltage‐controlled oscillator (VCO). The quadrature ILFD uses TAI‐C tanks and cross‐coupled switching pairs, the dynamic threshold MOSFETs (DTMOSs) are used to lower the supply voltage and power consumption. The ILFDs were fabricated in the 0.18‐μm 1P6M CMOS technology. At the supply voltage of 1.8 V, at the incident power of 0 dBm the locking range in the Colpitts ILFD in the divide‐by‐4 mode is about 5.45 GHz, from the incident frequency 3.75 to 9.2 GHz. The core power consumption is 4.93 mW. At the supply voltage of 1.4 V, at the incident power of 0 dBm the locking range in the QILFD in the divide‐by‐4 mode is about 7.41 GHz (103.6%), from the incident frequency 3.45–10.86 GHz. The core power consumption is 7.56 mW. The die area is 0.541 × 0.534 mm2. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3229–3232, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23933