Abstract
This letter presents an analog median filter with ultra-low-voltage supply and extremely low-power consumption. The structure of the median filter is based on comparators built by current limiting transconductance amplifier (OTA). In order to achieve high transconductance and large input range the proposed CMOS structure of the OTA is based on a cascade of two differential stages where the differential pairs exploit the dynamic threshold MOSFET (DTMOS) technique. The proposed structure of OTA is capable to work with 0.5V supply voltage and consumes 30nW with simple CMOS circuitry. The design and simulation of the median filter have been performed in Cadence environment using the 0.18μm CMOS TSMC process. The simulation results prove the functionality and the attractive features of the proposed circuit.
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