An Ultra-Low-Power and High-Gain Four-Quadrant Analog Multiplier Based on Dynamic Threshold MOSFET (DTMOS)

Abstract

This paper presents a low-voltage, ultra-low-power, and high-gain four-quadrant analog multiplier (FQM) using dynamic threshold CMOS (DTMOS). The proposed multiplier consists of the Gilbert cell along with the cross-coupled structure. The cross-coupled structure increases the gain of the circuit by creating a negative resistance. Thanks to the sub-threshold region, DTMOS, and tailless design, the proposed multiplier has a low supply voltage and consumes ultra-low power. What makes the DTMOS transistor attractive is the low threshold voltage and high transconductance due to the positive source-body voltage. The proposed FQM is self-bias and has been designed using ten DTMOS transistors. It has been simulated with the HSPICE tool using TSMC 90nm CMOS technology parameters. The proposed multiplier has a voltage gain of 7.5dB, -3dB bandwidth of 330kHz, the maximum THD of 4.5%, and 400mV of the supply voltage. The load capacitance is 100fF, and the estimated area is 4.4μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while consuming 66nW of power.