A novel SOI-DTMOS structure from circuit performance considerations

Abstract

The performance of a partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DT-MOS) is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOI DTMOSFET structure (drain/source-on-local-insulator structure) is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.