Dynamic Random Access Memory Research Articles

Interfacial engineering of ZrO2 metal-insulator-metal capacitor using Al2O3/TiO2 buffer layer for improved leakage properties

ABSTRACT The continuous scale-down of dynamic random-access memory (DRAM) requires shrinkage of high aspect ratio metal-insulator-metal (MIM) capacitance along with the successful suppression of its leakage current to maintain desired levels of charge storage and retention. As the dimensions of stacked insulating dielectric and metal electrodes in the MIM capacitor are currently <10 nm, interfacial mixing has a large impact on the reliability of the capacitor. This is because defects and secondary interface oxides significantly alter the physicochemical properties of MIM capacitors. The methodology required to characterize ultrathin interfaces in relation to the performance of MIM devices is highly challenging due to its physical and chemical complexities of interface between dielectric and electrode. In this study, a ZrO2-based dielectric film and its interface (with an ultrathin TiO2/Al2O3 buffer layer) are analyzed using angle-resolved X-ray photoelectron spectroscopy (ARXPS), spectroscopic ellipsometry (SE), and temperature dependent I–V analysis for a DRAM MIM capacitor. The composite dielectric layer included either Al2O3 on the bottom or Al2O3/TiO2 between the TiN electrode and ZrO2. This study suggests an effective metrology approach to characterize ultrathin MIM capacitors and the important role of interfacial stabilization using a buffer layer for the effective control of leakage current.

Characterizing and Mitigating Soft Errors in GPU DRAM

While graphics processing units (GPUs) are used in high-reliability systems, wide GPU dynamic random-access memory (DRAM) interfaces make error protection difficult, as wide-device correction through error checking and correcting (ECC) is expensive and impractical. This challenge is compounded by worsening relative rates of multibit DRAM errors and increasing GPU memory capacities. This work uses high-energy neutron beam tests to inform the design and evaluation of GPU DRAM error-protection mechanisms. Based on observed locality in multibit error patterns, we propose several novel ECC schemes to decrease the silent data corruption (SDC) risk by up to five orders of magnitude relative to single-bit-error-correcting and double-bit-error-detecting (SEC-DED) ECC, while also reducing the number of uncorrectable errors by up to 7.87×. We compare novel binary and symbol-based ECC organizations that differ in their design complexity and hardware overheads, ultimately recommending two promising organizations. These schemes replace SEC-DED ECC with no additional redundancy, likely no performance degradation, and modest area and complexity costs.

CYBER SECURITY IN INDUSTRIAL CONTROL SYSTEMS (ICS): A SURVEY OF ROWHAMMER VULNERABILITY

Increasing dependence on Information and Communication Technologies (ICT) and especially on the Internet in Industrial Control Systems (ICS) has made these systems the primary target of cyber-attacks. As ICS are extensively used in Critical Infrastructures (CI), this makes CI more vulnerable to cyber-attacks and their protection becomes an important issue. On the other hand, cyberattacks can exploit not only software but also physics; that is, they can target the fundamental physical aspects of computation. The newly discovered RowHammer (RH) fault injection attack is a serious vulnerability targeting hardware on reliability and security of DRAM (Dynamic Random Access Memory). Studies on this vulnerability issue raise serious security concerns. The purpose of this study was to overview the RH phenomenon in DRAMs and its possible security risks on ICSs and to discuss a few possible realistic RH attack scenarios for ICSs. The results of the study revealed that RH is a serious security threat to any computer-based system having DRAMs, and this also applies to ICS.

Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.

Nickel Pyrophosphate Nanoparticles: Synthesis, Structural, Thermal, Spectroscopic, and Dielectric Studies

Nickel pyrophosphate is very popular material having applications in energy storage devices as well as supercapacitors. In this study, a surfactant-mediated approach was adapted to synthesis nickel pyrophosphate nanoparticles. The prepared material was subjected to structural, optical, electrical and electrochemical property studies. Peak broadening in the powder XRD pattern confirmed the nanostructured nature and monoclinic structure of pure [Formula: see text]-Ni2P2O7nanoparticle with unit cell parameters of [Formula: see text] [Formula: see text], [Formula: see text] [Formula: see text], [Formula: see text] [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]. Pure [Formula: see text]-Ni2P2O7samples calcined at 300∘C, 600∘C, 900∘C show monoclinic structure. The average crystallite size and the internal strain were evaluated using Scherrer’s formula and Williamson–Hall (W-H) respectively. The TEM analysis confirmed the particle size in the range of 5–10[Formula: see text]nm for Ni2P2O7. Presence of symmetric and asymmetric stretching vibrations of P–O–P and PO3was determined by FT-IR spectroscopy. The spectral range of 210–1200[Formula: see text]nm was employed by the UV-NIR absorption spectroscopy, and the energy band gap calculated from Tauc’s plot is found to be 5.38[Formula: see text]eV for pure Ni2P2O7. The EDAX analysis confirmed the elemental composition. The TGA analysis reveals that the sample becomes anhydrous and remain stable beyond 600∘C. The higher dielectric constant observed for the sample is promising for semiconductor, DRAM memory devices and ceramic capacitors. The a.c. conductivity increases with increasing frequency and follows Jonscher’s Power law. On the basis of Jonscher parameters, small polaron QMT conduction model is prevailing. The cyclic voltammetry study was carried out to ascertain the application potential for supercapacitors.

A Timing-Based Split-Path Sensing Circuit for STT-MRAM.

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (VDD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal VDD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time.

Design of novel 3T ternary DRAM with single word-line using CNTFET

Ternary logic system is the most promising and pursued alternative to the prevailing binary logic systems due to the energy efficiency of circuits following reduced circuit complexity and chip area. In this paper, we have proposed a ternary 3-Transistor Dynamic Random-Access Memory (3 T-DRAM) cell using a single word-line for both read and write operations. For simulation of the circuit, we have used Carbon-Nano-Tube Field Effect Transistor (CNTFET). Here, we have analyzed the operation of the circuit considering different process variations and showed the results for write delay, read sensing time, and consumed current. Along with the basic DRAM design, we have proposed a ternary sense circuitry for the proper read operation of the proposed DRAM. The simulation and analysis are executed using the H-SPICE tool with Stanford University CNTFET model.

The Performance Enhancement of PMOSFETs and Inverter Chains at Low Temperature and Low Voltage by Removing Plasma-Damaged Layers

In this work we report on the improvement in cold temperature characteristics of PMOSFETs and inverter circuits by removing the plasma-damaged layer of the source/drain contacts. We removed the plasma-induced damage on the Si using a simple in situ Si soft treatment technique. We found by transmission electron microscope (TEM) analysis that the damaged amorphous layer reduced from 52 Å to 42 Å and 35 Å with a treatment time of 10 and 20 s, respectively. As a result, the resistances of both the n+ and p+ contacts decreased for all contact sizes and the standard deviations at the cold temperature were suppressed by 45%. At −25 °C, the saturation current of the PMOSFET increased by 3% and the propagation delay time (tPD) decreased by 2%. The tPD increases by 19.3% when the temperature decreases from 85 °C to −25 °C, and the operating voltage decreases from 1.2 V to 0.95 V at the same time. However, this increase can be reduced to 17% by applying the soft treatment for 10 s. This simple and short time process will be considered essential for both mobile applications and automotive applications of dynamic random access memory (DRAM) devices requiring a low-voltage and low-temperature operation.

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-VT 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400MHz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs(others' work in K. Sharma et al.and A. Goyal et al.)the retention power of the proposed GC-eDRAM is around 80-90% lower.

DRAM-based Physically Unclonable Functions and the Need for Proper Evaluation

Dynamic Random-Access Memory (DRAM)-based Physically Unclonable Functions (PUFs) are a part of the Physical Layer Security (PhySec) domain. Those electrical PUFs are memory based and exhibit a high availability, Shannon Entropy, low energy consumption and high amount of Challenge Response Pairs (CRPs). Because of those properties, the DRAM PUF is a promising approach for security applications in the Industrial Internet of Things (IIoT) context as well as securing the Sixth-Generation (6G) Wireless Systems and edge computing.&#x0D; DRAM, with its most common one-Transistor one-Capacitor (1T1C) architecture, and as a volatile memory is embedded in almost every modern computing unit. Regarding the PUF security applications, four main types of applications are currently distinguished in the scientific community: Retention Error, Row Hammer, Startup and Latency PUFs. Thereby these differ in their procedure in how responses are generated as well as by the physical mechanisms. Each of them with varying properties in terms of availability, reliability, uniqueness and uniformity.&#x0D; To examine this, and to obtain comparable results, this work proposes to compare the four different DRAM-PUF types i) with the same metrics of evaluation and ii) implemented on the same DRAM cells. This represents both the difference with regard to the work done in the literature and the added value of this work presented. As far as known, there is no work to date that performs the intended evaluations using the same evaluation platform under the identical conditions. However, this is required for comparable results.&#x0D; This consistent comparison is ensured by a self-developed and implemented evaluation platform, which is accordingly equipped with a significant number of DRAMs. By an appropriate high volume of measurements, a corresponding resolution will be given. Monitoring the environmental conditions prevents from wrong interpretations caused by environmental influences but also provides useful context information. Furthermore, a detailed technical and physical background will be described. The results of this approach will assist by the consideration of which DRAM-PUF is appropriate in which (environmental) conditions and thereby provide a guideline for practitioners.

Physical Layer Security: About Humans, Machines and the Transmission Channel

In an increasingly interconnected and globalized world in which the volume but also the confidentiality of transmitted content is becoming ever more important, trust, confidence and trustworthiness are of fundamental importance. Particularly in human societies, this trust is established, sustained and strengthened by personal relationships and experiences. But, in a globally connected world with Cyber-Physical Production Systems (CPPS), Industrial Internet of Things (IIoT) and Digital Twins (DTs), these personal relationships do not longer exist. (Remote) access to systems is possible from anywhere on the globe. However, this implies that there have to be technical solutions to detect, identify and acknowledge entities -people and machines- in the networks and thus to establish an initial level of trust.&#x0D; Especially since the proliferation of appropriate use-cases, Physical Layer Security (PhySec) is becoming increasingly popular in the scientific community. Using systems' intrinsic information for security applications provides a lightweight but secure alternative to traditional computationally intensive and complex cryptography. PhySec is therefore not only suitable for the IIoT and the multitude of resource-limited devices and sensors, it also opens up alternatives in terms of scalability and efficiency. Moreover, it provides security aspects regarding the entropy H and Perfect Forward Secrecy (PFS).&#x0D; Therefore, this work provides insight into three major branches of PhySec: i) Human - Physically Unclonable Functions (PUFs) ii) silicon/electrical - PUFs, and iii) Channel-PUFs. Based on the PUF operating principle, the silicon derivatives consider the electrical properties of semiconductors. Individual and uninfluenceable deviations during the manufacturing process result in component-specific behavior, which is described in particular for Static- and Dynamic Random Access Memory (S-/DRAM). Following this PUF principle, human characteristics -biological, physiological and behavioral features-, are used to recognize and authenticate them. With respect to the wireless channel, the characteristic properties of electromagnetic wave propagation and the influences on the wireless channel -diffraction, reflection, refraction and scattering-, are used to achieve symmetric encryption of the channel.&#x0D; In addition to the "conventional" wireless PhySec, especially the development of the Sixth Generation (6G) Wireless Systems, opens up a wide range of possibilities in terms of PhySec, for example in relation to Visible Light Communication (VLC), Reconfigurable Intelligent Surfaces (RIS) and in general the application of frequencies in the (sub)THz range.&#x0D; Thus, the work provides an overview of PhySec fields of application in all areas of the IIoT: in terms of humans, machines, and the transmission channel.

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes.

This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.

Regulating the electrical resistive switching behaviors of polyimides through different steric hindrance substituents on 2,7-position of tetraphenyl fluorene diamines moieties

Three novel polyimides (PI(TPF-Br BPDA), PI(TPF-Ph BPDA), and PI(TPF-Ph-OMe BPDA)) with tetraphenyl fluorene (TPF) were synthesized and tested. The laboratorial results showed that the constructed electronic devices exhibited different memory behaviors due to the different steric hindrance substituents (bromine atom, phenyl, and 3,5-dimethoxyphenyl) in 2,7-position of TPF molecule. The memorizers based on PI(TPF-Br BPDA) and PI(TPF-Ph BPDA) presented volatile dynamic random access memory (DRAM) feature with turn-on voltages of −2.39 and +1.45 V, as same as −1.71 and +1.74 V, separately. However, the PI(TPF-Ph-OMe BPDA) based apparatus exhibited non-volatile write-once read-many-times memory (WORM) behavior with turn-on voltage of −1.13 V, due to the more charge traps of 3,5-dimethoxyphenyl moieties and higher dipole moment. The switching mechanism was verified by quantum simulation of energy level, electrostatic potential (ESP) surface and dipole moment. These results indicated that the electrical memory performance of the synthesized TPF-based PIs could be adjusted by modifying the electron donor structure.

ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM

Advances in the density and capacity of dynamic random access memories (DRAMs) have resulted in emerging reliability issues. The error correction code (ECC) is widely used as a promising technique to improve the reliability of high-density memories. For this reason, many studies on ECC have been conducted to address the increased cell failure rates. However, conventional ECCs have shown limited achievements owing to area, latency, and power overheads. This study proposes ECC architecture reusing content-addressable memories (CAMs) for obtaining high reliability in DRAM, which can be called ECMO. The proposed architecture reuses CAMs in built-in self-repair, which can be used to repair memory hard faults during manufacturing as data storage to replace error data words. This achieves high reliability along with an additional 9155 h DRAM lifetime. Nevertheless, it can be implemented with a 3.04&#x0025; area overhead due to the reuse of CAMs. Moreover, only 0.21 ns is added to the critical path. Furthermore, the power overhead is 0.1&#x0025; compared to the total power consumption of DDR3 and DDR4.

Task‐aware swapping for efficient DNN inference on DRAM‐constrained edge systems

Object detection at the edge side is a common task in various environments. The deployment of convolutional neural networks in intelligent edge systems is very challenging because of the highly constrained main-memory space. This study aims at operating neural networks with a reduced memory requirement. The basic idea is that tasks of the same type would involve the same critical subnetwork. We propose identifying the critical network connections by considering the importance of channels. During runtime, the proposed method detects the task types and timely swaps the model parameters of the critical subnetworks from the external storage into dynamic random access memory (DRAM). Compared with conventional network pruning, the proposed approach further reduced the DRAM requirement by 34.6% while maintaining a high inference accuracy.

An Insightful Assessment of 1T-DRAM With Misaligned Polarity Gate in RFET

The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ge 6~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> , retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented.

Dependency-Aware Tensor Scheduler for Industrial AI Applications: Dymem—An Aggressive Data-Swapping Policy for Training Nonlinear Deep Neural Networks

Artificial intelligence (AI) applications based on deep neural networks (DNNs) have been widely applied in industry, e.g., in natural language processing and computer vision, among other fields. Researchers and industry practitioners typically use GPUs to train complex, hundred-layer deep learning (DL) networks. However, as the networks become wider and deeper, the limited GPU memory becomes a significant bottleneck, restricting the size of the networks to be trained. In the training of DNN-based AI applications, the intermediate layer outputs are the major contributors to the memory footprint. Various data-swapping techniques, such as the offloading and prefetching of intermediate layer outputs, are proposed to overcome the GPU memory shortage by utilizing the CPU dynamic random-access memory (DRAM) as an external buffer for the GPU.

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

Artificial intelligence (AI) and machine learning (ML) are revolutionizing many fields of study, such as visual recognition, natural language processing, autonomous vehicles, and prediction. Traditional von-Neumann computing architecture with separated processing elements and memory devices have been improving their computing performances rapidly with the scaling of process technology. However, in the era of AI and ML, data transfer between memory devices and processing elements becomes the bottleneck of the system. To address this data movement issue, memory-centric computing takes an approach of merging the memory devices with processing elements so that computations can be done in the same location without moving any data. Processing-In-Memory (PIM) has attracted research community’s attention because it can improve the energy efficiency of memory-centric computing systems substantially by minimizing the data movement. Even though the benefits of PIM are well accepted, its limitations and challenges have not been investigated thoroughly. This paper presents a comprehensive investigation of state-of-the-art PIM research works based on various memory device types, such as static-random-access-memory (SRAM), dynamic-random-access-memory (DRAM), and resistive memory (ReRAM). We will present the overview of PIM designs in each memory type, covering from bit cells, circuits, and architecture. Then, a new software stack standard and its challenges for incorporating PIM with the conventional computing architecture will be discussed. Finally, we will discuss various future research directions in PIM for further reducing the data conversion overhead, improving test accuracy, and minimizing intra-memory data movement.

Extracting the Secrets of OpenSSL with RAMBleed.

Concomitant with the increasing density of semiconductors, various attacks that threaten the integrity and security of dynamic random access memory (DRAM) have been devised. Among these, a side-channel attack called RAMBleed is a prolific one that utilizes a general user-level account without special rights to read secret information. Studies have reported that it can be used to obtain OpenSSH secret keys. However, a technique for deriving the Rivest–Shamir–Adleman (RSA) secret keys used in OpenSSL under realistic parameters and environments has not been reported. We propose a method that uses RAMBleed to obtain OpenSSL secret keys and demonstrate its efficacy using the example of an Apache server. The proposed method exploits the fact that, in the operation of an Apache server that uses OpenSSL, the RSA private keys are deployed on DRAM at a set time. Although the result of reading this secret information contains a few errors, error-free secret information is obtainable when it is used with RSA cryptanalysis techniques. We performed a series of attacks incorporating RAMBleed and eventually retrieved the OpenSSL RSA private key, indicating that secret information is obtainable with high probability. The proposed method can easily and externally be executed without administrator privileges on a server using DRAM that is vulnerable to RAMBleed, showing that RAMBleed is also a major threat to OpenSSL.

Equivalent oxide thickness scalability of Zr-rich ZrHfO2 thin films by Al-doping

With ultra-miniaturization of dynamic random-access memory (DRAM), it is very important to achieve equivalent-oxide-thickness (EOT) scaling of capacitors using materials applied to mass production. Compared to ZrO2, Zr1-xHfxO2 has a high possibility of improved electrical properties by doping in wide composition ranges. Therefore, we investigated the effect of Al-doping on electrical properties of Zr-rich Zr1-xHfxO2 thin films. Up to Al-doping of 2.1%, the leakage current was significantly improved without degradation of the dielectric constant, and it was possible to reduce the EOT by 0.12 nm in the leakage current specification applicable to DRAM capacitors.